Cascade Microtech Breaks Through the Barriers of 3D Test

Cascade Microtech Breaks Through the Barriers of 3D Test

For quite some time, the lack of cost-effective test solutions for 2.5D interposers and 3D stacked ICs (3D SICs) has been at the top of many industry experts’ laundry list of ‘what’s-holding-up-commercialization for 3D’. First, there are technology issues: fine-pitch probing, pin count, contact force and the phenomenon of weak I/O drivers. But bigger than that, the cost of 3D test is a major barrier because conventional approaches determine cost per pin, which becomes cost prohibitive when pin count increases to 10,000 pins or more. Cascade Microtech has had these barriers on its radar ever since 2000, when Eric Strid, co-founder of the company, started to engage the market on what 3D TSV technologies would mean for the test community. It is this early-stage thinking and awareness that has helped Cascade Microtech get where it is today – commercializing cost-effective solutions that address critical technology issues for 3D test. These solutions were not reached alone, however, but in deep collaboration with imec’s 3D integration group and other joint development partners.

3D Test

Figure 1: With the Cascade Microtech/imec team (L-R back): Steve Harris, executive VP, Cascade Microtech; Erik Jan Marinissen, Principal Scientist imec; Botho Hirschfeld, PhD, product marketing manager, Cascade Microtech; and Joerg Kiesewetter, Ph.D., engineering manager, Cascade Microtech, Debbora Ahlgren, VP of Marketing at Cascade Microtech; Francoise von Trapp, Q3D, 3D InCites

At the invitation of imec’s Erik Jan Marinissen (who also happens to be on the 3D InCites technical advisory board) and Debbora Ahlgren, VP of Marketing at Cascade Microtech, I visited the company’s test lab at imec, to get the back-story, learn more about the technology, and see the tool in action. The group also included Steve Harris, executive VP, Cascade Microtech; Botho Hirschfeld, PhD, product marketing manager, Cascade Microtech; and Jörg Kiesewetter, PhD, engineering manager, Cascade Microtech (Figure 1).

Historically, Cascade Microtech has been a technology-focused rather than a commercially-focused organization. “We used to be a company of engineers dedicated to solving specific customer problems,” said Ahlgren. “Now those same engineers are focused on solving market problems.” The timing couldn’t be better, because as 3D integration technologies approach mainstream manufacturing, solutions initially developed to solve customer problems have become market problems.

According to Harris, the current market perception is that micro-bumps used for 3D IC assembly cannot be probed for testing without causing significant damage to the bump that would affect yields at subsequent steps. The second perception is that even if it could be done, it would be too expensive.

There was consensus among the group that despite what the OSATs say about taking a yield hit and not performing pre-bond or partial-stack testing, when it becomes clear that the OSATs will be bearing the cost of non-working parts, they will make the choice to test. “We don’t need to convince customers about the partial stack testing,” said Ahlgren “They’ve been waiting for a breakthrough. imec and Cascade Microtech have innovated that breakthrough that allows them to test a partial stack before committing that last expensive component.”

“Our goal has been to prove that probing micro-bumps really is an alternative. Our collaboration with imec is part of reaching that goal,” said Harris. “We’ve solved the technology issues by demonstrating that our Rocking Beam Interposer (RBI) technology can successfully probe 50 and 40µm pitch bumps. Others have developed technologies but I don’t think they are cost-effective. Our solution has been validated by imec and the cost-effectiveness was modeled using imec’s cost estimator.”

Rocking Beam Interposer for 3 DTest

RBI leverages thin film lithography process, which results in a high-precision, fine-pitch, low-force contactor engine. (courtesy of Cascade Microtech)

RBI leverages Cascade Microtech’s thin film lithography process, which results in a high-precision, fine-pitch, low-force contactor engine, explained Ahlgren (Figure 2). It addresses cost-of-test by changing the paradigm of how cost is determined. Rather than being calculated as a cost-per-pin unit, as with conventional probe tip technology, RBI’s cost is determined per device. According to Harris, because other MEMS-based probe contact manufactures hand-assemble their probe tips, the approach is cost prohibitive when dealing in these high-pin-count probers. “When contacts are lithographically patterned by the hundreds of thousands, this model can be challenged,” he said.

The RBI technology has demonstrated low force probing on 40um pitch Wide-I/O structures and 20um copper pillars without causing any damage. “We are currently working with key industry partners who are helping us prove out the technical capabilities before going to the broader market “ noted Ahlgren. “This technology has been on our roadmap for a while, and we expect to be ready as the market need for it emerges.”

The company’s roadmap calls for providing key enabling products and solutions for 3D test in three distinct ways. The RBI technology, coupled with innovations in pitch, pin count and contact force will create a viable technical offering, explained Ahlgren. The development of a replaceable contact engine, which will come later and requires incremental innovation, will add cost effectiveness. Lastly, a proprietary space transformer technology that enables even finer pitches by allowing fine pitch pads for probing to fan out to the larger pitch requirements of test equipment rounds out the integrated solution Cascade Microtech plans to bring to its customers.

“We saw the writing on the wall and began innovating one dimension at a time,” explained Ahlgren, “First RBI, then the probe card itself with the space transformer and replaceable contact engine, and the CM300 probe station with its high accuracy probe capability and noise immune environment, allows us to bring an engineering characterization tool to market.”

The issue with weak I/O drivers is also unique to 3D stacks, and is the next challenge that Cascade Microtech and imec plan to tackle together. Each bump on a die generates just enough power to drive the electrical signal to the next bump die in the stack. Testing requires enough power to drive the signal off the chip to the test board. The solution is not to increase the power to the bump, because the low power benefit of 3D would be lost. “We’ve recognized the challenge, have IP filed, and are working with our ATE partners to solve it,” said Harris. The work is being vetted with industry partners, and the company is working with imec to validate the approach.

We also talked a lot about the path that brought this company and this research institute to this juncture. The collaboration between Cascade Microtech and imec dates back to 2005. A joint development project in 2010 extended beyond probe stations to include the field of probe cards and has netted some breakthrough achievements, including the recent success with contacting 50 and 40µm pitch micro-bumps.

While the company has delivered engineering probe stations and probe cards for design characterization and production applications for 25 years, it was the acquisition of the SUSS MicroTec’s probe station division in 2010 that put them in position to move forward with 3D test solutions. Hirschfeld and Kiesewetter were part of that development team that came with SUSS.

“Both Cascade Microtech and SUSS MicroTec have a background in leading-edge test equipment, so when they came together in 2010, the installed base was huge for all wafer formats,” explained Kiesewetter. “We used to be arch rivals. Now we’re one big happy family.”

Kiesewetter also explained about the company’s collaboration efforts that began in the 3D space alongside SUSS in 2010 as part of a European funded project called Efficient Silicon Multi-Chip System-in-Package Integration (ESIP): Reliability, Failure Analysis and Test, in which a subset of tasks was related to testing 3D structures. Other research institutes and companies involved in this project included imec, Fraunhofer EMFT, Feinmetall, and Team Nanotec. The project wrapped up in June 2013 and was awarded the ENIAC Innovation Award 2013; the successful testing of 50 and 40µm pitch micro-bumps on TSVs came out of this work.. Additionally, the CM300 is the first product based on the collaborative efforts of SUSS MicroTec Test Division and Cascade Microtech as one company. So far, the company has shipped over 15 tools, and the CM300 was awarded Best in Test for 2014.

“Without the community that imec created and the benefit of European funds, I don’t know if we would have the platform for what this can become,” said Ahlgren. Thus, the importance of collaboration in bringing 3D integration technologies to commercialization is proven once again. ~ F.v.T.

Coming up next…. The Cascade Microtech Test Lab Tour