As this year’s 3D IC Test Workshop unfolded (September 12 & 13, 2012), one thing became increasingly clear to me: the challenge of probing microbumps is an item of critical concern in 3D test.
During the panel discussion on test requirements for 3D ICs, Saman Adham of TSMC Canada, noted that currently, microbump probing is extremely difficult and we need a better way to probe. Qualcomm’s Amer Cassier added that the reason for the challenge is the number of bumps needing to be probed, and poor signal integrity due to weak drivers. A stronger signal is needed to accurately test the interconnect capabilities of the microbumps.
The plot thickened during the Friday panel, How Will 3D Testing Change the 3D Supply Chain?, when Global Foundries, TM Mak, explained that with 2.5D and 3D IC technologies, cost/yield is paramount for 3D IC to survive and prosper, and that the level of known good die (KGD) “goodness” needs to increase. “97% is not good. 99% may not even be good enough when hundreds of dollars worth of good silicon is thrown away if you have a single bad die or even bad via.” he noted. “How do you get close-to-perfect silicon with lousy sort capabilities?”
Mak identified missing technologies and business processes affecting the 3D IC supply chain, among them probe test, test IP for non-contact I/O test methodologies, limitations of power-constrained sort, and yield ownership. Specific to probe test, Mak expanded on Cassier’s explanation of signal integrity and weak drivers, explaining that although there is some progress reported in tight-pitch probing technologies, the wide bus and the I/O are not designed for driving current to automated test equipment (ATE). Additionally, custom active probe cards and load boards are too expensive.
Amkor’s Gerard John explained his company’s approach to the 3D IC test flow. He identified three test points in the assembly flow, and assessed the risk levels of each. He explained that Test Point 0 uses a standard wafer probe to assess KGD, and carries low and medium level risk. The same is true for Test Point 2 – final package test. The issues clearly reside with Test Point 1, which tests for known good TSVs. Gerard identified these areas as medium to high risk, particularly with regard to low leakage and low R current measurements, and with vertical probe cards using Kelvin probes to touch down on very small pads on TSV bumps.
To gain a better overall understanding of the problems and the potential answers, I turned to Imec’s Erik-Jan Marinissen for some explanations. He started with the basics:
TSVs form the interconnect from the front side of the die to the backside. Microbumps on the TSV pads form the interconnect between the two die. Today’s bumps are 40-50µm, and the technology exists to test them. However, explained Marinissen, 10µm diameter TSVs can be made, so the bottleneck in density lies with the microbump, therefore there is pressure to reduce the microbump size. He also stressed the importance of pre-bond testing before stacking to ensure yield.
Testing the C4 bumps on the bottom die is easy because they can be accessed from the bottom. The challenge comes in testing the microbumps on the top die. Pitches are too small for today’s technology. As noted previously in this post, manufacturers like TSMC and GlobalFoundries say they can’t probe microbumps below 50µm.
On the upside, there are lots of projects in the works to address these issues. Both Formfactor and Cascade Microtech presented papers on their probe technologies at the workshop, and earlier in the week at the International Test Conference, TSMC presented the probe test approach they take for their Chip on Wafer on Substrate (CoWoS) process flow.
TSMCs approach is targeted to testing its passive interposer used in CoWoS. The interposer is the lowest cost component of CoWoS, and stack yield depends upon interposer yield. Since it is not possible to test for KGD on the passive interposer because it only contains microbumps, TSVs, optical interconnects and C4 bumps, TSMC has come up with a “pretty good die” (PGD) solution that relies on optical interconnect probing from the front side through sacrificial pads, and TSV testing through C4 probing on the backside.
But according to Marinissen, this is insufficient. “Probing on test pads doesn’t really accomplish what you need because you can’t tell if the microbumps work,” he explained. “You’re adding a capacitive load for no good reason, which requires extra design time and extra space.”
For some time, imec has partnered with with Cascade Microtech to develop tools and processes that would allow for probing directly on the microbump to initiate pre-bond test. The goal was to make good electrical contact with minimal damage to the microbump so as to affect the interconnect. In July, they reported success in probing 25µm diameter bumps using Cascade Microtech’s 300mm probe station and an advanced version of its Pyramid Probe technology. However, this is just the first step in a multi-step process before it can be used in volume manufacturing.
Formfactor, also a manufacturer of wafer probe technologies, has embarked on a similar mission with memory manufacturer, Elpida, with its Nanopierce contactor.
Marinissen clarified the primary differences for me. Both Formfactor and Cascade Microtech have probed the 40-50µm-pitch microbumps of the JEDEC Wide-IO DRAM interface. While FormFactor has demonstrated touching the four Wide-IO channels (4×300 bumps), the approach is limited to singulated die in a socket. Cascade and imec have only touched down on a single Wide I/O channel (300 bumps), but using a probe card solution, stepping over an entire 300mm wafer with a probe station.
In his presentation, Very Low Damage Direct Testing of Micro-Bumps for 3D IC Integration, Formfactor’s Onnik Yaglioglu explained that the Nanopierce contactor was developed to probe microbumps and micropillars for KGD and known good stacks (KGS). He reported that they have demonstrated full area contact and simultaneous probing of microbumps at 40-50µm pitch. Yaglioglu explained that the technology is highly scalable to achieve very dense pitch. Further, test set-up allows for precision alignment of the die under test to the contactor.
In his presentation, Signal Integrity Design for Wide I/O and 3D TSV IC Test at Wafer Probe, Cascade Microtech’s Ken Smith addressed that greater challenge described previously by Adham and Cassier. He detailed work being done on the signal integrity issue, identifying three elements to address including signal routing density, clean power delivery, and weak I/O driver limitations and progress in each area. He especially highlighted a breakthrough with the weak driver issue that involves pre-charging the tester interconnect to a large percentage of the predicted output level. This gives the weak driver the necessary boost to reach the right voltage level so that the microbump’s interconnect capability can be accurately tested by ATE. This is still in early stages so we can expect to hear more about this as the work unfolds.
These are just a few examples of the work presented at this year’s 3D IC Test Workshop. Proceeding of this event will be made available in the near future. ~ F.v.T.