09/12/2013 - 09/13/2013 -All Day

Location: Disneyland Hotel

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image002The Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST) takes place September 12-13, 2013 and will feature Nick Ilyadis, VP & CTO of Broadcom’s Infrastructure & Networking Group as an invited keynote speaker. Ilyadis will open the event with a talk entitled 3D Solutions in the Coming Age of Terabit Communication.

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products.

In addition to a robust technical track, this year’s event extends beyond R&D and academia to include participation from the semiconductor industry at large, with the keynote, 2 panels, and one special session devoted to industrialization of 3D IC test solutions.

Thursday’s opening program will feature a panel discussion, Requirements for 3D Volume Production Testing. As the industry prepares for commercialization of 3D ICs, test requirements will vary based on the device being manufactured, and the manufacturer of that device. Panelists from various sectors of semiconductor manufacturing including memory, logic, foundries, and fabless will share their requirements on defect detection, design-for-test, test equipment, and test costs with the test community and answer critical questions. Panelists from AMD, Micron, Qualcomm, Samsung, SanDisk, TSMC, and Xilinx will participate. The panel is moderated by Bill Eklow – Cisco Systems, USA.

3D IC stacking is more intricate than 2D assembly and requires elaborate testers to perform fully functional test. Built-in self-test adds cost and takes die real estate. Going to 3D means re-thinking the test strategy from what it was in the past, especially in terms of economics. Friday morning’s panel, How Will 3D-Testing Change the Test Supply Chain? features panelists from Synopsys, Advantest, GLOBALFOUNDRIES, imec, Tel Test Systems, and Amkor who will discuss will discuss strategies to address the unique circumstances surrounding 3D IC testing.

Wrapping up the 3D IC Workshop will be a special session featuring the nominees and winner of this year’s 3D InCites Awards category for test and reliability tools and equipment. Moderated by Françoise von Trapp (Queen of 3D), each panelist will briefly introduce the product that was nominated for the award, and discuss the technical merits. The remainder of the session will be in a Q&A discussion format, focused on these innovative solutions for 3D IC test and reliability including design-for-test solutions, probe card and test contactor technology, built-in-self test for memory, test handlers, and inspection and metrology for TSV reliability. Companies represented include Cadence, Mentor Graphics, Cascade Microtech, Formfactor, Multitest, and Rudolph Technologies.

The 3D Test Workshop takes place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.

Download the final agenda here.  For registration and hotel information, visit the 3D Test Workshop web site.