3D test

Probe Test for 3D Integration: A Thousand Mile Journey

Probe Test for 3D Integration: A Thousand Mile Journey

When we look back at the last 10 years, it’s really been a series of baby steps to move the commercialization of 3D integration technologies forward. There is no single pivotal event that catalyzed the 3D evolution. Like the Chinese philosopher, Lao Tzu said, “do the difficult things while they are easy and do the great things while they are small. A journey of a thousand miles begins with a s... »

New Solution for Testing Chips Prior to 3D Stacking

New Solution for Testing Chips Prior to 3D Stacking

Stacking chips on top of each other (aka 3D stacking) is a well-known approach to make more compact and powerful systems. Until now, it was impossible to probe the large arrays of fine-pitch micro-bumps on advanced chips before stacking. This had a negative effect on the compound yield (because of including faulty dies in the stack). Imec, together with FormFactor (formerly Cascade Microtech), has... »

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3D IC Test: Now and The Road Ahead

Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I consider test standards and test challenges, which include known-good-die and testing stacked die. The two main goals of 3D IC test are to improve the pre-packaged test quality and to ... »

3D-TEST Workshop Does What Its Name Says: Concentrates On 3D-Test

3D-TEST Workshop Does What Its Name Says: Concentrates On 3D-Test

Virtually all scientific and industry forums on 3D have “3D design-for-test” and/or “3D test” on the topic list of their Call for Papers, but typically at the very bottom of that list, and in practice they focus on 3D technology and/or 3D design and do not offer much 3D-test content. If you don’t believe me, check for yourself how often the word “test” appears in the programs of ... »

Designing in 3D? Don’t Make These DFT Mistakes

Designing in 3D? Don’t Make These DFT Mistakes

The semiconductor industry hasn’t adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the ‘scaling’ camp rather than moving it to the ‘3D’ camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers hav... »

Xcerra™ President and CEO to Join Panel Discussion at Semicon West

Xcerra™ President and CEO to Join Panel Discussion at Semicon West

Xcerra™ Corporation announced that Dave Tacelli will join the panel discussion “Testing into the Future” at SEMICON West, scheduled to take place July 8 to 10 in San Francisco. The panel discussion will be part of the TechXpot North session “Seeking Growth” on Tuesday, July 8, 2014 from 10:30 am – 12:30 pm hosted by Collaborative Alliance for Semiconductor Test (CAST). This session wil... »

3D Test

Cascade Microtech: In the imec 3D Test Lab

My visit to imec to meet with the Cascade Micorotech and imec 3D Test collaboration team included a tour of the 3D test lab to see the CM300 in action, so we suited up for Class 1000 cleanroom and stepped inside. Generally we would have had to prep for class 100 or higher for the test environment, but thanks to nifty new FOUPs that have a class 1 microenvironment to protect the wafers, we at least... »

Cascade Microtech Breaks Through the Barriers of 3D Test

Cascade Microtech Breaks Through the Barriers of 3D Test

For quite some time, the lack of cost-effective test solutions for 2.5D interposers and 3D stacked ICs (3D SICs) has been at the top of many industry experts’ laundry list of ‘what’s-holding-up-commercialization for 3D’. First, there are technology issues: fine-pitch probing, pin count, contact force and the phenomenon of weak I/O drivers. But bigger than that, the cost of 3D test is a maj... »

3D TSV Test Approaches: Outlook for 2014

3D TSV Test Approaches: Outlook for 2014

Metrology, process control, and electrical test are key enablers for the success of the semiconductor industry. 3D integration using TSVs offers new challenges in this area that need solutions. There seems to be industry consensus that it is extremely difficult to perform a wafer-level test that ensures the complete functionality of the TSVs. There are ideas about how to perform 3D TSV test with ... »

Multitest’s Next Phase: An Interview with Reinhart Richter

Multitest’s Next Phase: An Interview with Reinhart Richter

This past July, I visited Multitest’s San Jose location to learn about the company’s activities in 3D IC test, as well as gain a better understanding of the company’s Plug & Yield™ philosophy, which spans handler, contactor and load board technologies. Earlier this month, the company announced its acquisition by LTX-Credence, along with its sister company, Everett Charles Technolog... »

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