Virtually all scientific and industry forums on 3D have “3D design-for-test” and/or “3D test” on the topic list of their Call for Papers, but typically at the very bottom of that list, and in practice they focus on 3D technology and/or 3D design and do not offer much 3D-test content. If you don’t believe me, check for yourself how often the word “test” appears in the programs of the upcoming IEEE 3D-IC or RTI 3D-ASIP conferences. And so, while friend and foe agree that test challenges are among the key hurdles that need to be overcome to enable the significant role 3D stacked ICs are predicted to play in tomorrow’s semiconductor products, it apparently takes an audience of test engineers to really address the 3D test issues. And that is the unique role that the 3D-TEST Workshop has taken.
The 2014 edition of 3D-TEST (in full: the IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits) took place in Seattle, Washington on October 23 & 24. Since its start in 2010, 3D-TEST has been organized in conjunction and co-located with the IEEE International Test Conference (ITC), the world’s premier test conference and hence the largest gathering of researchers, engineers, and managers that take an interest in test technology. At the start of the week, ITC’14 presented relevant 3D-test content (with two half-day tutorials, two paper sessions, and an IEEE Std P1838 fringe meeting), but for the true 3D-test geeks this merely served as warming-up toward the real highlight of the week: A workshop featuring 24-hours of dedicated 3D-TEST!
As this was the first lustrum edition of 3D-TEST, there was, for the first time, an award ceremony at the 5pm start of the workshop. Several members of the organizing committee have served for all consecutive five editions of the workshop in the same role and were awarded a “TTTC Meritorious Service Award” for their volunteering efforts: Yervant Zorian (Synopsys) as General Chair, Erik Jan Marinissen (imec) as Program Chair, John Potter (ASSET-Intertech) as Arrangements Chair, Françoise von Trapp (3DInCites) as Publicity Chair, and Gert Jervan (TU Tallinn) as Web Chair. Also, a 3D-TEST 2013 Best Paper Award was given to Makoto Nagata and Satoshi Takaya (Kobe University, Japan) and Hiroaki Ikeda (ASET, Japan) for their paper entitled “In-Place Signal and Power Noise Waveform Capturing Within 3D Chip Stacking”; a journal version of their 3D-TEST 2013 paper will be published in the magazine, IEEE Design & Test.
After the opening ceremonies, the workshop was kicked off well by a visionary keynote talk from Brion Keller, Senior Architect at Cadence Design Systems, appropriately titled 3D Rock from the Sun. He talked about “existing 3D pursuits” such as imager/processor stacks, 3D-FPGAs, memory stacks (HBM, HMC, WIO) that allow “super-charged” memory interfaces to “CeePee and GeePee”, but also elaborated on future technologies such as monolithic 3D and micro-channels for use in liquid cooling and capturing solar energy. Keller’s end conclusion: “Products will appear when the demand is there.”
Next up was a status update on IEEE P1838, the 3D-DfT standard-under-development, presented by four members of the P1838 Working Group. Erik Jan Marinissen (imec), WG Chair, presented an overview of the Working Group’s activities, which is divided over three so-called “Tiger Teams”; a similar overview presentation is available for download. Subsequently, Adam Cron (Synopsys), WG Vice Chair, presented the work in “Tiger Team 1” on a serial control interface, based on a 3D extension of IEEE Std 1149.1. Cron was followed by Teresa McLaurin (ARM), Vice Chair of “Tiger Team 2”, who concentrated on P1838’s Die Wrapper Register (DWR) which is largely inspired by IEEE Std 1500’s Wrapper Boundary Register. Last but not least was Sandeep Bhatia (Google), Member of “Tiger Team 3”, who outlined P1838’s Flexible Parallel Port. This informative session lasted till about 7:15pm, time for a well-catered reception and informal networking.
The next day had an early start, with breakfast at 7am and the workshop sessions resuming at 8am. The day started off with presentations by three PhD students who have worked in the domain of 3D-test and are close to graduation: Sergej Deutsch (Duke University), Bing-Yang Lin (National Tsing-Hua University, Taiwan), and Bei Zhang (Auburn University). This session gave a good impression of ongoing academic research and provided the students the opportunity to increase their job prospects; one actually included his entire resume in the workshop’s hand-out!
In the sequel of the workshop, two paper sessions with in total seven papers were included. These papers touched on diverse topics as cross-die built-in self-repair for 3D-stacked Wide-I/O DRAM, power supply noise, boundary scan with embedded delay lines, ESD testing, magnetic field imaging for electrical fault isolation, wafer sort of interposer dies, and TSV leakage. The full workshop’s program (as well as back-issues of the workshop’s Electronic Workshop Digest) is published here.
3D-TEST traditionally also features a Table-Top Demos and Poster session. This year, demos were on display from Cascade Microtech, STAr Technologies, Synopsys, and the University of Siegen (Germany). The discussions at the demo tables were rather animated.
Prior to the lunch break, the first of the workshop’s two panel sessions was held, entitled “3D Memories: What Is Coming And How Are We Going To Test That?”. Panel moderator Françoise von Trapp (3D InCites, “Queen of 3D”) had planned to make this an interactive session with live on-line audience voting on prepared provocative statements; unfortunately, the hotel’s WiFi infrastructure let us down and the lack of cell-phone coverage did not constitute a viable alternative. Despite these technical hiccups, the panel session was informative, entertaining, and an absolute success. This was certainly due to the strong panel line-up:
- Betty Prince – CEO at Memory Strategies International – a recognized expert in memory technology and design, with a recently released book entitled “Vertical 3D Memory Technologies”
- Bob Patti – CTO at Tezzaron Semiconductor – pioneer in 3D memory stacking and with lots of hands-on experience
- Jon Colburn – Principal DfT Engineer at NVidia – responsible for defining the DfT architecture for NVidia’s 2.5D and 3D products
- Gary Fleeman – Industry expert with many years of past experience at Advantest and involved in the JEDEC Wide-I/O standardization committee.
There seemed to be general consensus among the workshop attendees that it is an important step forward that DRAM makers have become aware of their responsibility toward facilitating stack-level interconnect testing, by having made the step to include boundary-scan-like DfT features in their products. It was remarked that the gate-level description format of those DfT features would best be standardized, for the benefit of automatic test pattern generation.
Herb Reiter, President of eda2asic Consulting and well-recognized missionary for the 3D EDA eco-systm, gave a stimulating invited presentation entitled, What a Difference a Year Makes. In this talk, Reiter looked both back and forward about one year. His list of major (2.5D/3D-related) industry achievements and milestones over 2013 and 2014 is impressive and a clear sign that 3D technology is ready for take-off. (In that sense, the color of the 3D-TEST polo shirts, which were green this year, in contrast to being red in 2012, was apparently well chosen!) According to Reiter, the 3D future looks bright, with applications as 4k/8k video and the Internet of Things providing drivers for new business opportunities.
Prior to the 3D-TEST 2014 workshop closure, the second panel session took place. In a (successful) attempt to retain the audience on Friday afternoon till the very end of the workshop, the panel session discussed today’s hottest topic in 3D test: 2.5D-SICs: Do We Need To Test The Interposer, And If So, How?”. Under leadership of panel moderator Jan Vardaman (TechSearch International), an all-star line-up debated this topic.
- Said Hamdioui – Associate Professor at TU Delft – Developed ‘3D-COSTAR’, a tool for assessing 3D test-flow trade-offs and their effect on overall stack quality and cost
- Gerard John – Technical Director Test Development at Amkor Technologies – Involved in interposer test for various customers
- Choon-Leong Lou – CEO at STAr Technologies, Taiwan – Sells test equipment for engineering and product purposes
- Amitava Majumdar – Principal Engineer at Xilinx – The first company to have a real 2.5D product out in the market
- TM Mak – Director 2.5D/3D DfT Strategy at GLOBALFOUNDRIES – Noted that in an interposer, “TSV shorts” are not really shorts and hence that redundant TSVs do not always improve the yield.
It was said that defects are more likely to occur in the micro-joints and less in the BEOL and TSVs in the interposer. This would indicate that pre-bond testing of interposers would not really be required. However, not all panelists agreed; while it is challenging to test interposers (and especially their vertical interconnects) prior to stacking, the cost price of the active dies that will be stacked on top of the interposer can make it worthwhile nevertheless.
For some of us, the discussion continued in a good Seattle seafood restaurant that same evening. For all of us, the next meeting will be at 3D-TEST 2015: October 8+9 in the Disneyland Hotel in Anaheim, California (again, in conjunction with ITC)!