SEMICON West and the Electronic System (ES) Design West were, for the first time, co-located at the Moscone Center in San Francisco, from July 9 to 11, 2019. In addition to most keynotes, I reported about here, This blog talks about some in-depth technical presentations on test and the progress many companies made in support of “More than Moore” technology.
The Test Vision Symposium
The most impressive technical presentations were at the Test Vision Symposium. To truly appreciate the progress wafer probe and test experts have made, allow me to recap some of the major challenges systems-in-package (SiPs) have in store for test experts: In single-die ICs, the final test yield is primarily determined by the die. Defects in the relatively lower cost and lower complexity package substrate and/or intra-chip connections are rarely the source of IC failures.
Multi-die ICs comprise more than just a costly collection of dice for performing digital, analog, RF, memory, and MEMS functions. Such a system-level solution also includes large, pricey interposers and a package substrate with multi-layer interconnects, integrated passives, and many through-silicon vias (TSVs) and relatively high pin/ball counts, to guarantee power and signal integrity – plenty of opportunities for defects.
Because the SiP final test yield is the product of all the yields of these building blocks, they need to be thoroughly tested individually before they can be assembled. However, exhaustive testing of all individual components to achieve “known good die (KGD)” has proven not to be technically feasible and/or not economical. In addition, rework to fix defective multi-die ICs has proven to not be practical.
Therefore the best strategy for creating high-quality, multi-die ICs cost-effectively is clearly to test every component thoroughly, before assembly. Testing partially assembled SiPs is also a good idea to achieve high yields at final test and with-it reliable products at acceptable unit cost. It also makes economic sense for very complex assemblies. Even better is exhaustive testing/probing at the wafer stage and/or of singulated dice.
The Test Vision Symposium demonstrated that our industry’s test experts and their management are fully committed to supporting More than Moore solutions and are developing technologies to exhaustively test/probe dice at the wafer stage and when singulated.
Wafer and die-level testing require tiny probe-pins. An impressive presentation, delivered by Norihiro Ohta, Nidec-Read Corp in Kyoto, Japan, and co-authored by Pete Rogan, Nidec SC TCL in Phoenix, AZ, focused on a range of tiny MEMS contactors (down to 1µm diameter) contained in springs, to control probe pressure and to rotate the probe-tip to remove possible oxide coating on a probe pad. (Figure 1).
Tuesday afternoon’s keynoter, Mike Slessor, CEO of FormFactor, focused his presentation on the most critical challenge for multi-die ICs: Exhaustive probing at the wafer stage and of singulated dice.
Slessor explained that KGD is a nice idea, but, depending on the actual design may not be practical for technical and/or cost reasons. See Figure 2. He pointed out that interposers, as they are getting larger and more complex finally have redundant TSVs. They need to be tested and can be repaired, just like high-bandwidth memories (HBMs). Then it makes sense to mount additional and expensive dice on them. In addition, Slessor recommended that multi-die IC designers should consider more and larger dedicated probe pads as well as redundant logic circuitry to enable higher manufacturing yields, lower test cost and lower unit cost (Figure 3).
Hasegawa-san from Advantest talked about another very important technology to enable our industry’s migration from a low margin component supplier to a high-value system-level solutions vendor: System-level test (SLT). First, he explained single die IC test on automatic test equipment (ATE), then SLT, then positioned SiP test in-between, called it a hybrid system-level test and explained the SiP trade-offs in(Figure 4).
John Kibarian, CEO of PDF Solutions, delivered the Test Vision keynote on Wednesday morning. He emphasized that electronic products are being assembled using more and more complex devices (Figure 5). To meet the requirement for security, reliability, performance, power, cost, etc., he emphasized that it’s very important to establish good cooperation with the designers and across the entire supply chain, utilize digital twins and diagnostic capabilities for yield enhancement/debug.
Teradyne’s Ken Lanier started his presentation with a surprising message: Bit-coin mining consumes more power today than all of Switzerland. In his talk, Then Lanier focused on the challenges of providing multiple, stable DC voltages to the load-board and device under test (DUT) and how to solve them.
Nikunj Mehta from Falkonry, explained how machine learning (ML) can and will make a lot of difference on a test floor: ML can identify quickly the circuit elements and parameters impacting yield and help to accelerate production ramp-up.
Gert Hohenwarter from GateWave Northern, emphasized the importance of considering return loss when testing RF designs. His presentation prepared the audience for the next wave of challenges: Testing 5G phones and Lidar systems in volumes.
Provisions for redundancy, self-test, self-repair are getting cheaper to implement
Before leaving the test topic, let me jump to the answer Stanford professor Subhasish Mitra gave me when I asked him during Monday’s Heterogeneous Integration Roadmap (HIR) session about how redundancy improves test yields.
“Multi-core and multi-die ICs are distributed systems and can offer redundancy almost for free, even allow self-repair,” he said. He suggested we encourage system and IC designers to architect multi-core and multi-die ICs in a way that they offer redundancy and allow test experts to utilize it to increase yield, reduce unit cost and accelerate production ramp-up. In general, as we use more and more parallelism in our logic circuits, designing in redundancy will become more cost-effective than taking the otherwise likely yield losses.
Every SEMICON West visitor faces one, practically insurmountable challenge: Where to focus, which sessions to attend, how to get the most out of the many excellent, but parallel events at SEMICON. I wish I would have had a twin, to send him/her to interesting sessions I couldn’t attend myself. To mitigate this drawback of a rich program, SEMI makes many presented slides available. This allows me to briefly summarize some of the sessions I couldn’t attend.
Jan Vardaman from TechSearch, Jim Handy from Objective Analysis, Mario Ibrahim from Yole, Mario Morales from IDC and Mark Patel from McKinsey talked about the market outlook from technical and/or business perspectives.
Vardaman highlighted the key benefits of heterogeneous integration and emphasized that major IC packaging suppliers offer many different types of IC packaging technologies. While following Moore’s Law, a.k.a. “jumping to the next node” always made it easy to improve performance, power, and lower cost, determining the technically best – and most cost-effective – IC packaging solution, requires significant information gathering, planning efforts, a.k.a. “Pathfinding”, constructive dialog and very good cooperation between silicon and package design experts.
Figure 6 was presented by Ibrahim. It shows how many different types of sensors autonomous driving will need and in how many different ways they’ll assist a driver to keep people safe inside and outside of the vehicle. To enable the vehicle to quickly react to such sensor information, lots of edge computing is needed.
What this diagram doesn’t show is all the additional electronics needed to have the vehicle communicate with other vehicles nearby, with a city’s infrastructure, a car’s manufacturer, a logistics center of the company who owns the vehicle, etc. Bottom line: Many opportunities are developing for selling reliable and cost-effective semiconductors into this market segment. Complementing all this hardware with software updates and services may become an even bigger opportunity.
Tuesday’s Media Lunch
Dave Anderson presented a number of important points that will not only impact the media business but our lives. For example:
Organizations, like corporations and governments, can only change slowly (logarithmically) while technologies, like AI, ML, 5G, Blockchain and communication platforms change our world very fast (exponentially). They offer many new opportunities as well as challenges and need to address – ideally – proactively.
Agreed-upon standards and best practices are important for managing the increasing complexities and need for cooperation, across the entire supply chain. Case in point: SEMI announced the completion of their 1000s manufacturing standard at SEMICON West and is looking forward to facilitating more standards that reduce cost, risk and time to profit.
The cost of publishing is dropping significantly. The means of creating content are getting cheaper and easier to use. How will the flood of (real and fake) news impact customers and, in turn, the increasing number of publishers?
SEMICON West 2019 was another impressive event that offered both very broad and in-depth information.
I look forward to next year’s SEMICON West because:
- The Design Automation Conference (DAC 2020) will be co-located and help to bring the manufacturing experts and EDA/Design experts closer together and enable both camps to work more efficiently individually and collectively.
- After a slow growth 2019 and early 2020, during July’s SEMICON West we’ll get a much better view of our industry’s mid and long-term future,
- The current trade tensions will (hopefully) be mitigated by mid-2020, giving the semiconductor industry a clearer view of future opportunities and make investment decisions easier.
Thanks for reading…Herb