Making Progress with 3D IC Design and Test

Making Progress with 3D IC Design and Test

Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for  2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool and design flow changes need to be evolutionary, rather than revolutionary.”

As Mutschler notes, a 2.5D configuration is evolutionary while 3D IC is revolutionary. The long-held position by many of the EDA vendors has been that existing design flows are sufficient for 2.5D and until 3D ICs are commercialized, there is no need for a completely new flow. Why? Mike Gianfagna, VP Marketing at eSilicon explained that 2.5D can be designed with existing flows because they are incremental. “when you look at full 3D, there’s a whole raft of new issues that you never had to deal with (with 2.5D), such as stress management, thermal management and chip-level density.”

To get the design-for-test perspective, Mutschler tapped into Stephen Pateras at Mentor Graphics, who explained that test for 2.5D is easer because contact points are exposed. In 3D stacks they may be hidden, and require “a convoluted signal path test starting on one side of the package and ending on the other,” writes Mutschler. Ultimately, she noted, “While the tools and approaches may be evolutionary, the actual application of those tools requires a radically different approach.”

Speaking of 3D IC test, Mentor Graphics and different approaches; according to a feature post that appeared recently in EE Journal, written by Ron Press, Etienne Racine and Martin Keim, of Mentor Graphics, solutions for 3D test are available today. The article, “A Flexible Strategy Test Strategy for 3DIC”  describes “a test strategy for 3D ICs based on a plug-and-play architecture that allows die, stack, and partial stack-level tests to use the same test interface, and to retarget die-level tests directly to the selected die within the 3D stack.” This is possible because according to the authors, “the fundamental requirements of a test strategy for 3D ICs are the same as for traditional ICs—portability, flexibility, and thoroughness.” The main difference, they explain, is that in a 3D stack, only the TAP on the bottom die appears. In this strategy, test is managed through that bottom TAP, which enables the TAPs of the next die in the stack and so on. What’s also notable is that this strategy is based on and integrates existing IEEE 1149.1 and IEEE 1500 standards, but expands beyond their individual possibilities.

The article goes on to explain in detail how the authors approached die level test, testing 3D stacks, external DRAM, and lastly testing between the stacks. The key take away is that this strategy works today because of the flexibility of the IJTAG Standard they used to structure the test architecture. However, 3D IC test standards, test requirements, and the types of external memories being used are still evolving, and this will likely affect future methodologies.

Both this posts piqued my interest today, because on March 28, 2014 at the DATE 2014 3D Workshop, I will be moderating a panel discussion that debates the question, Are Slow Standardization and CAD-Tool Development Hindering the Progress of 3D IC Design and Integration? A loaded question, for sure. If you’re attending DATE 2014, you won’t want to miss this lively and interactive discussion. Based on what I’ve read here, I know where I’m leaning but I’m not quite ready to give away my opinion. Check back with me in a few weeks. ~ F.v.T.