Latest Posts
Siemens and Intel Foundry Collaborate on New Tools Certifications and EMIB/3D-IC innovation
Siemens Digital Industries Software announced today that its ongoing collaboration with Intel Foundry has established a new Electronic Design Automation...
Siemens Collaborates with Samsung Foundry to Expand 3D-IC Enablement Tools
The collaboration includes the optimization of other EDA solutions for Samsung Foundry’s newest processes Siemens Digital Industries Software announced that,...
Siemens to Transform Engineering Workforce of the Future With Industry Credential Program
Siemens Digital Industries Software announced today that it has created a new program to credential students and recognize career readiness,...
Siemens Delivers End-to-end Silicon Quality Assurance for Next-generation IC Design Projects
Siemens Digital Industries Software today introduced Solido™ IP Validation Suite software, a comprehensive, automated signoff solution for quality assurance across...
Cadence and Intel Foundry Collaborate to Enable Heterogeneous Integration with EMIB Packaging Technology
Cadence and Intel Foundry have collaborated to develop and certify an integrated advanced packaging flow utilizing Embedded Multi-die Interconnect Bridge...
Siemens Qualifies IC Design Solutions for Intel Foundry Processes
Siemens Digital Industries Software today announced that its IC design solutions — Calibre® platform tool for integrated circuit (IC) design...
An Organic Package Designer’s Guide For Transitioning to FOWLP and 2.5D Design
Numerous package designers possess extensive hands-on experience in crafting organic FR4/HDI build-up BGA/LGA substrates. They have mastered the design guidelines,...
An EDA Perspective on Today’s Advanced Packaging
In my alliance management roles at electronic design automation (EDA) companies, I arranged many presentations to convey the benefits of...
Wally Rhines Discusses the Importance of EDA and Design at IWLPC 2018
At this year’s International Wafer-level Packaging Conference, almost 1000 semiconductor experts from all parts of the supply chain gathered at...
EDPS 2017: NOT the usual Electronic DESIGN Process Symposium
When planning the 24th EDPS, the organizing committee, chaired by Shishpal Rawat, former Intel executive, took a number of bold...
3D IC Test: Now and The Road Ahead
Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I...
‘Tis the Season for the 3D ASIP Multi-Die IC Design Tutorial
While the shopping malls and specialty stores in and around San Francisco were packed with people hunting for Holiday presents,...
Why Do We Need Assembly Design Kits for Packages?
In our last article, we talked about a project we participated in to test the feasibility of an assembly design...
Mentor Graphics: Xpedition Package Integrator
Xpedition® Package Integrator provides a holistic co-design methodology that automates planning and optimization of connectivity from a chip through multiple...
Can Path Finding be used in the Production Environment?
In previous posts, I have discussed various scenarios when Path Finding can be used. All were focused on the early...
3D ASIP Pre-Conference Symposium brings together Design and Process for 3D ICs
Despite efforts to leverage the one hour time difference from Phoenix to San Francisco to my advantage, I arrived on...
Are there still Gaps in 3D IC Readiness?
Good news! At last week’s GSA 3D IC Packaging Working Group Meeting, July 23, 2014, Jan Vardaman uttered the words...
Should EDA vendors, OSATS, and their customers cooperate more?
Last week, I attended the packaging-focused 64th Electronic Components and Technology Conference (ECTC) 2014 in Orlando. This week I spent...
