EDA Tools

EDPS 2017: NOT the usual Electronic DESIGN Process Symposium

EDPS 2017: NOT the usual Electronic DESIGN Process Symposium

When planning the 24th EDPS, the organizing committee, chaired by Shishpal Rawat, former Intel executive, took a number of bold steps EDPS was traditionally held in the spring. We moved EDPS to the fall because that’s a time when more new IC projects are being planned. After many years of holding it in Monterey, we moved EDPS to Milpitas to make it more easily accessible for Silicon Valley folks... »

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3D IC Test: Now and The Road Ahead

Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I consider test standards and test challenges, which include known-good-die and testing stacked die. The two main goals of 3D IC test are to improve the pre-packaged test quality and to ... »

‘Tis the Season for the 3D ASIP Multi-Die IC Design Tutorial

‘Tis the Season for the 3D ASIP Multi-Die IC Design Tutorial

While the shopping malls and specialty stores in and around San Francisco were packed with people hunting for Holiday presents, a very dedicated crowd of 3D IC developers and users from all over the world got together near San Francisco, for the 12th 3D ASIP conference, which featured, once again, the multi-die IC Design Tutorial. Conference presenters reviewed the progress made in 2015 and discus... »

Why Do We Need Assembly Design Kits for Packages?

Why Do We Need Assembly Design Kits for Packages?

In our last article, we talked about a project we participated in to test the feasibility of an assembly design kit (ADK) for package design verification. This time, we’d like to delve a little more into the reasons why assembly design kits are needed. Naturally, one of the reactions to our article was “But I already have requirements from my package house. Why do I need an ADK?” True, packa... »

Mentor Graphics: Xpedition Package Integrator

Mentor Graphics: Xpedition Package Integrator

Xpedition® Package Integrator provides a holistic co-design methodology that automates planning and optimization of connectivity from a chip through multiple packaging variables, while targeting multiple PCB platforms. Engineers can quickly and easily assemble complete cross-domain systems (IC, package & board) and drive ball map plans and pin optimization through a rule-based methodology. Te... »

Can Path Finding be used in the Production Environment?

Can Path Finding be used in the Production Environment?

In previous posts, I have discussed various scenarios when Path Finding can be used. All were focused on the early design process: implementation guidelines, robust design and process centering. But what if you have a design in production and ‘something’ happens; like a process is no longer available; a component must be replaced by another, yields become erratic, etc. Is there a role for Path... »

3D ASIP Pre-Conference Symposium brings together Design and Process for 3D ICs

3D ASIP Pre-Conference Symposium brings together Design and Process for 3D ICs

Despite efforts to leverage the one hour time difference from Phoenix to San Francisco to my advantage, I arrived on the scene at the 2014 3D ASIP Conference to find the morning Pre-conference Symposium on (Interposer) and 3D Design Tools and Flows already well underway. My absence did not go un-noticed by the first presenter, Bill Martin, E-System Design, or by the session organizer and fellow 3D... »

Are there still Gaps in 3D IC Readiness?

Are there still Gaps in 3D IC Readiness?

Good news! At last week’s GSA 3D IC Packaging Working Group Meeting, July 23, 2014, Jan Vardaman uttered the words I’ve been waiting to hear her say for quite some time. “Memory stacks with TSVs are here!” Vardaman cited three companies actively involved in new memory architectures, all of which involve stacking memory either with or without interposers – Tezzaron, Micron and Hynix. She ... »

Should EDA vendors, OSATS, and their customers cooperate more?

Should EDA vendors, OSATS, and their customers cooperate more?

Last week, I attended the packaging-focused 64th Electronic Components and Technology Conference (ECTC) 2014 in Orlando. This week I spent three days at the EDA-focused 51st Design Automation Conference in San Francisco. In addition to realizing that these two locations are about three thousand miles apart, I noticed that the packaging and EDA camps are still far apart in regards to share of mind ... »

Making Progress with 3D IC Design and Test

Making Progress with 3D IC Design and Test

Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for  2.5D and 3D IC design and test, and providing such a clear explanation in your post, “Evolution vs. Revolution”. In this 2-part post, Mutschler explores the EDA vendor arguments that “tool and design flow changes need to be evolutionary, rather than revolutionary.” A... »

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