‘Tis the Season for the 3D ASIP Multi-Die IC Design Tutorial

‘Tis the Season for the 3D ASIP Multi-Die IC Design Tutorial

While the shopping malls and specialty stores in and around San Francisco were packed with people hunting for Holiday presents, a very dedicated crowd of 3D IC developers and users from all over the world got together near San Francisco, for the 12th 3D ASIP conference, which featured, once again, the multi-die IC Design Tutorial. Conference presenters reviewed the progress made in 2015 and discussed challenges to be addressed in 2016, to broaden the use of ICs comprised of multiple dies, to additional market segments.

Why do I say “additional” market segments? Because the compelling performance-versus-power and form-factor benefits of multi-die ICs have already been demonstrated in vertically stacked dies, a.k.a. 3D memory cubes (HMC, HBM, DiRAM) and as interposer/substrate mounted dies, side-by-side, in computing, networking and graphics applications. If you consider a blazingly fast graphics card for your home PC as a consumer application, AMD’s Bryan Black outlined during this conference how he has even conquered this segment with an interposer solution that’s 3x faster than AMD’s previous graphics card. It’s in volume production, ready for your PC and costs only ~ $ 600,- at Amazon.com.

The biggest steps forward to expand the user-base for multi-die ICs have been made during 2015 with an impressive wave of cost-reduction efforts: Several manufacturers, including major foundries and assembly houses, presented how they have reduced cost by 1) eliminating TSVs in multi-die ICs and by 2) combining interposer and substrate into one component. In addition, instead of molding only several ICs in one manufacturing step, they have 3) enhanced the proven fan-out wafer-level packaging (FOWLP) technology to mold 100s of ICs, each with multiple dies reconstituted on a 12-inch wafer, simultaneously. Even more impressive were their announcements to complement wafer-level packaging with 4) panel-level packaging, to mold 1000s of IC simultaneously — to further increase throughput and drive down unit cost.

As current and potential multi-die IC users listen to success stories, like mentioned above, and realize that several major manufacturers are working very hard to drive down the unit cost of multi-die ICs, I am asked frequently by these users and also by the hard-working manufacturers: “What are EDA vendors doing to make it easier to plan and design cost-effective multi-die ICs?” They all know that user-friendly and high-productivity design flows not only minimize time to market, but also help designers to walk the fine line between costly over-design and risky under-design of ICs and systems.

To answer this very reasonable and timely question about if/how EDA vendors are complementing the enormous development- and cost-reduction efforts at IC manufacturers, I organized and moderated the EDA-centric 3D Design Tutorial on the first day of the 3D ASIP conference. I also compiled and distributed – at no charge for all tutorial attendees – a 300+ pages Multi-die IC Design Guide, with inputs from 25 important companies and organizations, providing for Multi-die ICs:

  1. Design tools
  2. IP building blocks
  3. Design services
  4. IC packaging-focused market research
  5. Industry-wide communication and standards developments.
  6. A number of universities, large R & D organizations and a well-known industry expert outline on 100+ pages their accomplishments and suggest how to utilize their expertise and resources to select the most appropriate technology, accelerate multi-die IC development programs and minimize system cost.

If you are interested in a softcopy of this document, please email me at herb@eda2asic.com.

Back to the Tutorial: “Design of Multi-die ICs using Interposers or Wafer-level Packaging.”

eSilicon’s Bill Isaacson presented first and demonstrated how his experience as ASIC designer and eSilicon’s track record help solving multi-die IC design challenges.

He stated that since 2011, eSilicon has developed for and with customers, a total of 7 interposer-based test chips. Some of them are in production today. Isaacson described several of these projects, combining ASICs, FPGAs and memory cubes on interposers and outlined how eSilicon addresses, jointly with customers, important topics like 1) the planning/partitioning step, 2) development of high speed and low power interfaces, 3) test and debug, 4) yield enhancement and 5) production qualification. The long Q & A session, following Isaacson’s presentation, demonstrated that eSilicon’s expertise is really appreciated and these topics are very relevant for the audience.

e-System Design’s Bill Martin focused on the importance of the planning/partitioning step for a multi-die IC design’s success. He compared this, commonly called “Pathfinding” step, with how a mountain climber maps out his/her path to the peak. Martin emphasized the increasing importance of the IC package for power- and signal integrity and showed how the Sphinx 3D Path Finder e-System Design offers can quickly and accurately enable SoC- and/or multi-die IC designers to evaluate multiple power-distribution-network (PDN) solutions and identify the best alternative. Martin showed several examples how their Sphinx 3D Pathfinder quickly identifies resonance points and helps to optimize TSV placement and a solid power-and-ground network, before time-consuming implementation steps are started.

ANSYSNorman Chang used a joint development program with Fujitsu’s Super Computer Division as an example of how to deploy the Apache BU’s tools to verify power and thermal integrity of large, vertically stacked dies. He emphasized how important thermal analysis, as well as power and signal integrity simulations, are to guarantee reliable operation of a 3D IC stack. Using this program, Chang outlined the entire analysis/simulation flow, from the essential modeling steps, through necessary iterations to evaluate how thermal and electrical parameters impact each other, to the final simulation runs. He also shared ANSYS’ vision for developing a flow to simulate how Power, Electrical, Electromagnetic, Thermal, ESD, Fluid and Structural parameters impact a system’s reliability.

Two speakers from Cadence Design Systems demonstrated the breath of Cadence’ multi-die IC design solutions.

Brandon Wang walked the audience through all essential design considerations, naming the appropriate Cadence tools, for thoroughly simulating an interposer-based (2.5D IC) solution. Using screen-shots and tools-generated reports, he showed how the suite of Cadence tools interacts in a die-interposer-package co-design sign-off flow.

Bill Acito complemented Wang’s interposer-focused and silicon-design-tools centric message with a more package-design-tools centric presentation. Acito also introduced Cadence’ capabilities for designing multi-die ICs for the rapidly growing latest generation of IC packages, using WLP technology. Equivalent to Wang, he emphasized the importance of die-package co-design and elaborated on how to manage currently different formats between IC and package design tools. Like all other speakers, Acito also pointed out that, due to constantly increasing pin-counts, signaling speeds and power densities, IC packaging’s role is drastically changing from a commodity item to an essential differentiator.

After a short networking break, Zuken’s Narayanan Terizhandur Varadharajan presented their system-level co-design solution, focusing on package-board interactions and how to use different mesh counts to keep a design’s data files and tools run-times manageable. Like previous speakers, Varadharajan also addressed the importance of thermal challenges from different angles and emphasized that power dissipation and the resulting thermal effects and challenges need to be estimated very early in a system design flow.

Last, but not least, two executives from Mentor Graphics, the sponsor of this tutorial, showed Mentor’s broad range of IC-package-board design solutions.

John Ferguson, IC verifications expert, and John Park, package and PCB solutions architect, gave an overview of Mentor’s design tools’ breath, emphasized the importance of a co-design flow across die-package-board and explained how different tools work together, across typically difficult to bridge domain boundaries. While Ferguson covered IC-centric topics, including the capability of Calibre 3DSTACK to accurately analyze die-to-die interaction in a 3D stack, Park focused on how on the co-design strengths of the Xpedition platform.

In summary, all presenters demonstrated that they have experience with multi-die IC design services or with developing —based on major customers’ requirements, point-tools — even complete design flows for interposer-based ICs, vertically stacked 3D ICs, and that they are finalizing, with advanced packaging leaders, wafer-level packaging design solutions.

We used the remaining minutes of the tutorial to give every attendee an opportunity to introduce him/her-self and briefly describe his/her role in context with multi-die IC design or manufacturing. This very well received request from the audience taught us several important points:

  1. About half of the total number of this year’s conference attendees’ found EDA topics important enough to come a day earlier to the conference and participate in this EDA-centric tutorial. They all expressed that they clearly understand the important role EDA plays in enabling multi-die IC market acceptance, accelerating time to profit and, most importantly, creating reliable and cost-effective IC- and system solutions.
  2. Most of the attendees traded their business cards for a USB stick with the 300+ pages Multi-die IC Design Guide.
  3. The attendees had many different roles and came from very diverse “corners” of the worldwide 3D IC ecosystem, e.g. EDA, IC design, package engineering, wafer fabs, IC assembly houses, equipment vendors, material vendors, system houses, IC market research, R&D organizations, industry organizations, universities and government. In their personal introductions they showed that they were quite experienced in the 3D IC domain and ready to support and/or utilize this technology in 2016, but most likely in lower volumes than at least one leading mobile device maker is committed to do.

Actually, now is the time for New Year resolutions! Allow me to share my 3D IC-related resolution with you:

“Bring EDA vendors closer together with material vendors and Multi-die IC manufacturers.”

Only closer cooperation between these two camps can improve modeling of a) material characteristics and b) capabilities of manufacturing flows. When driving the PrimeTime STA sign-off wave I learned very quickly that EDA tools are only as accurate and useful as their inputs. EDA tools and flows can significantly impact cost reductions and performance enhancements, if given up-to-date and accurate inputs, ideally encrypted. Let’s make 2016 the year of modeling!!! ~ Herb