The 3D Architectures for Semiconductor Integration and Packaging (3D ASIP) conference is one of the biggest (if not THE biggest) event focused exclusively on the 3D IC family of technologies. The December 2016 event was held even closer to San Francisco airport than in previous years. From the lobby of the SFO Marriott Hotel, we could see planes taking off and landing. Every smooth touch-down an... »
It’s 2017, and system-on-a-chip (SoC) is headed for a dielet. At least that’s my 2017 outlook, based on takeaways from some of the recent conferences I’ve attended, including, to close out 2016, 3D ASIP last month in Burlingame, CA. SoC has been packing on weight in recent years, and it’s beginning to show, to SoC’s detriment. For example, the old ISO defect density rules from my early I... »
While the shopping malls and specialty stores in and around San Francisco were packed with people hunting for Holiday presents, a very dedicated crowd of 3D IC developers and users from all over the world got together near San Francisco, for the 12th 3D ASIP conference, which featured, once again, the multi-die IC Design Tutorial. Conference presenters reviewed the progress made in 2015 and discus... »
As a cost modeling company, when we were asked to speak at 3D ASIP this past December, the initial topic choice seemed fairly obvious. We decided to tackle the question of whether the cost of 3D ICs will ever be low enough for HVM. We’ve done a lot of individual projects focusing on both interposer and 3D technology, so we have experience modeling both of those 3D architectures, but we have neve... »
Isn’t it interesting how different people attending the same event can come away with different perspectives? I attended last week’s 3D Architectures for Semiconductor Integration and Packaging (3D ASIP 2014), and came away feeling euphoric about what the 3D industry has achieved since last 3D ASIP, and all its promise for the future. After following the technology progress and believing in i... »
Despite efforts to leverage the one hour time difference from Phoenix to San Francisco to my advantage, I arrived on the scene at the 2014 3D ASIP Conference to find the morning Pre-conference Symposium on (Interposer) and 3D Design Tools and Flows already well underway. My absence did not go un-noticed by the first presenter, Bill Martin, E-System Design, or by the session organizer and fellow 3D... »
While other presenters for the 2013 3D ASIP session, “Evolution of 3D Technologies and Market Trends” took a more conventional approach to reporting the status of 3D integration, Jan Vardaman, TechSearch International gets the prize for originality and humor for playing the role of “professor” and delivering the 3D readiness report card, grading progress in the key challenge areas. Her app... »
For years, we’ve been talking about the performance and power benefits of 2.5D and 3D ICs. We’ve also been talking about the remaining challenges, and have steadily ticked off the technology-related ones. The “elephant-in-the-room” has been, and continues to be cost. But based on the messages of some key industry players who presented at this year’ 3D Architecture’s for Semiconductor I... »
The supply chain business model for manufacturing 3D stacked ICS has caused perhaps one of the hottest debates so far in commercializing 3D semiconductor processes. It’s easy to see why. Beyond the rather obvious question of who will own the liability of damaged devices, there’s a good deal of revenue at stake for those who make the investment in adding capacity for middle end of the line (M... »
Day Two of 3D ASIP and even though the conference opened with declarations that “3D is here” it’s clear after attending the sessions and hearing what all the presenters have to say, that this is a multi-dimensional situation. First, there are the vendors and suppliers, who have a lot at stake, having invested billions developing processes to get to this point. Then there are the manufacturer... »
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