It’s 2017, and system-on-a-chip (SoC) is headed for a dielet.

At least that’s my 2017 outlook, based on takeaways from some of the recent conferences I’ve attended, including, to close out 2016, 3D ASIP last month in Burlingame, CA.

SoC has been packing on weight in recent years, and it’s beginning to show, to SoC’s detriment.

For example, the old ISO defect density rules from my early Intel days still apply just as certainly in 2017 as they did in 1980; i.e. that for a given and constant random defectivity level in the wafer fab, larger chips will have much worse yields on the same process technology than will smaller die. wafer_dies_yield_model_10-20-40mm_-_version_2_-_en

Improved redundancy, added attention to design-for-manufacturing, and much lower random defect levels today notwithstanding.

And that’s considering the case of having all of the functional real estate on a big SoC design always active, meaning that it is always on or at least almost always being addressed or exercised, and thus always usefully employed.

What happens when you add His Dark Silicon to the mix? Here, designers intentionally add the capability to address individual portions of a complex piece of silicon logic and cause that portion to be shut down on command in order to avoid peak-activity overheating. As Zvi Or-Bach has reported, “’In a recent IEDM 2014 short course by ARM’s principal engineer, Greg Yeric, dark silicon was projected to account for ‘about one-third of total area in the 20nm technology node (including 16/14nm FinFETs), increasing to as much as 80% by the 5nm node.’”dark-silicon-zvi-dsi-0077-01

We are making big chips that are big because of added functionality only to have much of their functional area actually powered off at any given time to avoid cooking the silicon.

It’s a great workaround, but I’m going to argue that, even though dark silicon does work in practice, it is anything but an elegant solution in concept.

“Simplicity is the ultimate sophistication,” I read in “The Real Leadership Lessons of Steve Jobs.”

as-simple-as-possibleThat’s why I’m sold on the idea of dielets.

(You can read much more about dielets and interconnect fabrics in the work Professor Subu Iyer, UCLA, and colleagues have been publishing as part of the CHIPS consortium.)

(And there’s also this piece by FvT.)

(Or read about chiplet work, something similar, as published by Dan Green and colleagues at DARPA.)

(Dr. Green and Professor Iyer both spoke at 3D ASIP 2016.)

Whether you call them chiplets, or dielets, heterogeneously integrating very small devices using some kind of silicon-based (or glass-based) interconnect fabric is a pretty terrific idea from a cost perspective, and also from a performance one.

Smaller die = better die yield = lower cost die; heterointegration = performance advantages when you combine just enough silicon transistors from one chiplet with just enough compound semiconductor transistors from one dielet.

SoC, you would do well to seriously consider heading for a dielet in 2017.

From Santa Clara, CA, in the Year of the Rooster, thanks for reading. ~PFWchanticleer

Paul Werbaneth

Paul Werbaneth is a long-time Contributing Editor at 3D InCites. Since entering the semiconductor industry…

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