System-level Scaling: UCLA’s Answer to Extending Moore’s Law

System-level Scaling: UCLA’s Answer to Extending Moore’s Law

“We are at a crossroads. Current chip design is nearing its capacity. The time, expense, and effort needed to make major inroads have grown exponentially. We need a transformational shift in how our systems are designed and put together. Moore’s law is no longer about scaling a chip, but about scaling the system.” ~ Excerpt from the letter to attendees of the CHIPS kick-off meeting at UCLA.

This is the mission of the new Center for Heterogeneous Integration and Performance Scaling (CHIPS) that was launched with a kick-off meeting at UCLA on November 2, 2015. The day was devoted to educating members of the semiconductor industry about the center’s vision, with the goal of recruiting industry partners to participate in realizing CHIPS’ goal. I attended at the invitation of the center’s director, Subramanian (Subu) Iyer, distinguished chancellor’s professor in electrical engineering, UCLA.

Previously an IBM Fellow with the IBM systems and technology group in Hopewell Junction, NY, Iyer has been proselytizing about the need to focus on system-level scaling vs. CMOS scaling for years. “The last 30 years have been the most exciting period in human history for what we’ve been able to accomplish, but things are changing,” said Iyer. Rather than predicting the demise of Moore’s law altogether, Iyer says we just need to reinterpret the meaning to be more holistic.

Computing is transforming, and data is at the center of it all, explained Iyer. The trend is towards cognitive computing (Watson vs the human brain), and this is causing a power gap and interconnectivity gap that are co-related. “We can’t scale or way out of it,” he said. “Yogi Bera would have said, ‘if you can’t scale the chip, scale something else’.”

CHIPS provides the resources and team that brings these concepts to life. One advantage of establishing CHIPS in a university environment is the simultaneous development of a sophisticated manufacturing workforce that will take the ideas developed at CHIPS out into the market place.

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Iyer’s “µYodabot” modeled in origami.

Iyer says CHIPS is taking inspiration from the “app world” and intends to do for hardware what the smartphone revolution has done for software. While app start-ups seem to pop-up in Silicon Valley almost daily, how many chip start-ups have there been in the last five years? Zero, says Iyer. It takes $30-50M and three to five years to get a chip designed and integrated. The goal of CHIPS is to develop an environment for hardware that cuts that time to market by 5-10x and cut non-recurring engineering (NRE) by 10-20x by integrating heterogeneous elements. He sees this path extending to cyber-physical systems: “an autonomous “µYodabot” that thinks, walks, flies, swims, and does stuff…” he said.

Iyer’s vision is to take hardened IP silicon “dielets” and integrate them onto a silicon “interconnect fabric” to create a “mega Silicon on interconnect fabric” (SoIF) system. “We don’t need a 15B fab to do this,” he said, “90% of SoCs contain preexisting IP. We make it hard IP and put it on the shelf.” That leaves only 10% that has to be designed for interconnecting the dielets, which shouldn’t take that long. Iyer says these can be manufactured in $30-50M assembly operation, and envisions one of these “in every city in the world.” The CHIPS concept will help foundries streamline processes, and also integrate exotic materials (III-V compound semiconductors) with fine-pitch silicon.

To get around issues of scaling the package to the board, which has only seen modest success; in SoIF systems, there is no package. Iyer explained that traditionally, package and board have been scaled using machine shop dimensions- mils and inches. “We’ve decided we’re doing everything in microns,” he said.

After all, do we really need the package? “We’ve come to the conclusion that the package actually destroys the chip,” he noted. The only benefit to the package that Iyer sees is that it protects the chip thermally, but that can be handled by mounting the heat spreader directly on the chip. “We can scale the package by getting rid of it, and mount the bare die directly onto the board,” explains Iyer. Furthermore, in the SoIF scenario, the printed circuit board is replaced by Si interconnect fabric – (aka a silicon wafer) on which the dielets are “intimately” integrated electrically and in space. The final wiring level will be 2-10µm pitch, and the chips will talk to each other as if they are on the same chip.

Contrary to what some may think, Iyer says this technology is not a reinvention of the silicon interposer (and don’t even use the dreaded 2.5D term in his presence; it’s not that either). Why? Because an interposer is a piece of silicon that is intended to be an interface between the chip and the board, so still has to accommodate not only the die scaled to it, but is limited by the board scaling.

Achieving these goals is not without its challenges. Although Si is the best interconnect fabric, “the brittleness of Si is a challenge. How to interconnect is a humongous challenge,” says Iyer. Still, he sees these as surmountable challenges. With software defined hardware, he says they will be able to generate the interconnect fabric within a few hours.

Iyer says up until UCLA’s electrical engineering department saw merit in his vision, his idea has been met with skepticism. “People say it makes sense, but it will never happen, because you’re trying to change the way people think and the way they do things,” noted Iyer. “I think it will happen. And if we don’t do it, someone else will. The best way to affect change is to do it from within.” In the words of the µyYodabot – Try not. Do or do not, There is no try. ~ F.v.T

NOTE: This post is based on Subu Iyer’s presentation at the CHIPS Kick-off event. It, and the rest of the supporting presentations are available here on the CHIPS Website.