Subu: “I find the whole concept of 2.5D fairly atrocious. I have banned its use.”
Rao: “what are you going to call it?”
Subu: “Interposers, like God intended it to be.”
The exchange quoted above took place between Subramanian Iyer, PhD, Director, Systems Scaling Technology IBM, and co-chair of this year’s Global Interposer Technology Workshop (GIT2014), and Rao Tummala, director, 3D Systems Packaging Research Center, Georgia Tech, during the panel discussion last week at GIT 2015.
This was the fifth year GIT was held at Georgia Tech’s Global Learning Center, Atlanta, and it has continued to grow in attendees and content, as interposer technologies have continued to take center stage in the march to 3D Integration. This year’s theme focused on interposer technologies as enablers of heterogenous integration. As such, 200 attendees gathered from around the world to hear 41 presentations over 2.5 days; and they were all about the development of advanced interposer technologies, its progress, and applications.
Rao Tummala, Director, 3D Systems Packaging Research Center, Georgia Tech, set the stage, continuing on his quest for “System-level Moore” that he first discussed in September at IMAPS 2014. Riko Radojdic of Qualcomm, stirred the pot by calling for an R&D consortium focused on low cost packaging technologies for Si interposer modules to fill the gap between what exists at organizations like Georgia Tech’s PRC and industry. He cited imec’s model as a successful example of what’s been done in front-end and middle of the line consortiums to develop TSV processes. He says the industry needs a similar consortium of combined efforts of R&D, OSATS, and equipment and material suppliers to create a pilot line (not and applications lab) dedicated to such efforts to help bring down the cost of interposer and 3D IC technology.
Jan Vardaman, founder, TechSearch International commented that a successful consortium such as this required full commitment of its participants, and pointed out previous efforts had stalled due to lack of corporate commitment. Iyer sparred with Radojcic, pointing out that due to OSATs small profit margin, and therefore difficulty in capitalizing such a project, that company’s like Qualcomm might need to pony up if they want such a consortium to be created.
This became quite the topic of discussion over the remaining two days of the workshop, particularly after hearing about all the interposer and memory products either in production or ready to ramp from companies like Xilinx, IBM, Micron, Samsung, and sk Hynix, as well as Ron Huemoeller’s report of Amkor’s advances in interposer assembly. As there is much more to report from GIT 2014, I will focus on the details of these discussions in my next blog.
But I digress… back to the topic of this blog. For some time, has been after me to write a blog post about the ridiculousness of the term – 2.5D when what we really mean is Interposer technology. When he says he banned its use, he’s talking about in the department he runs at IBM. But what he would really like to see is a global banning of it as an industry term.
So what’s the big deal with calling it 2.5D (aside from the fact that there’s no such thing as half a dimension?) If you ask Phil Garrou, Consultants of North Carolina, he’ll tell you its because it was originally used by Ho Ming Tong at ASE as a joke when he said, in reference to interconnecting die to the package using through silicon vias (TSVs) through a passive interposer rather than stacking active die with TSVs.“we’re not at 3D ICs yet, we’re at 2.5D.” I concur with Garrou, because I was there and I heard the presentation.
Garrou defines interposer as “an electrical interface routing used to spread a connection to a wider pitch.” He maintains that by that definition, anything that is a package is an interposer, because it takes fine pitch interconnects and spreads them out to fit the larger pitch of the circuit board. I would argue that point slightly, because what differentiates today’s interposer configurations from classical 2D system-in-packages, (SiPs) is that Si interposers implement TSVs as the interconnect method for power, performance and form factor improvements. Classical packages do not achieve those same performance benefits, so if we’re going to drop the 2.5D, we need to still differentiate between packages and interposer technologies.
Perhaps the reluctance of some to drop the 2.5D moniker is because it takes away some designation as a 3D technology? I maintain that advanced interposer technologies that rely on a passive piece of silicon with TSVs between active die and the package is still a 3D architecture. Others claim that to be “True 3D” active die need to be stacked on active die. To that I say, whatever. Advanced interposers still apply the benefits of 3D integration by going vertical in architecture, and require TSVs to achieve these architectures. That’s 3D enough for me.
Ever since Subu and I talked about eliminating 2.5D from the industry lexicon at SEMICON Singapore, I’ve been making a concerted effort to use “interposer” in place of 2.5D. In covering GIT2014, I’m determined to stick to the plan, but it’s going to be a challenge, because “2.5D” pops up in many titles and in many discussions. So starting now, all “2.5D” on 3D InCites will be referenced as Interposers or 3D Interposers where applicable. When it comes to exact quotes, I will replace 2.5D parenthetically as (interposer). ~ F.v.T.