2.5D Interposer: A configuration where dies are mounted side by side on one side of a thin (~ 100 um) silicon, glass, or organic interposer using through silicon vias (TSVs), through glass vias (TGV) or through substrate vias (TSV), respectively through the interposer to connect the dies with the package substrate. Communication between the dies takes place via interconnect wires fabricated on the interposer.
3D Interposer: A configuration where dies are mounted on both sides of a thin silicon, glass, or organic interposer using TSVs or TGVs through the interposer. Communication between the dies takes place via interconnect wires fabricated on the interposer.
3D Integration: A very broad term that includes such technologies as 3D wafer-level packaging (3D WLP); 2.5D and 3D interposer-based integration, 3D stacked ICs (3D-SIC), monolithic 3D ICs, 3D heterogeneous integration, and 3D systems integration. In contrast: 3D transistors refers to FinFETs.
3D IC: A three-dimensional integrated circuit involves stacking dies and interconnecting them with through silicon vias (TSVs). Also used interchangeably with 3D Stacked ICs (3D-SICs).
3D MEMS: Three-dimensional microelectromechanicall system. Created when a MEMS device is interconnected to an IC in a vertical rather than side-by-side configuration.
3D SIC: Three Dimensional Stacked Integrated Circuit involves stacking dies and interconnecting them with TSVs. Often used interchangeably with 3D ICs.
3D SoC: A three-dimensional system-on-chip device involves partitioning a complex SoC into its functional parts, implementing these parts in two or more dies and then stacking them vertically, using TSVs as interconnects.
3D SiP: A three-dimensional system in package is created using wire bonding to interconnect system on chip (SoC) advanced CMOS with disparate technologies, e.g. combining logic and memory.
3D Systems Integration/Heterogeneous Integration: Refers to a 3D IC that contains all the functionality of a sub-system or entire system. It typically involves stacking disparate technologies such as RF, analog, MEMS, logic, and memory. It may or may not use an interposer.
3D WLP: A 3D integration technology based on wafer-level-packaging (WLP) infrastructure and technology, such as redistribution and flip-chip bumping. The 3D WLP vias correspond to interconnects at the bond-pad level.
Interconnectology: a system-level approach to the design and development of next-generation interconnect devices that adds value to the entire system architecture by positively impacting performance, form factor and power consumption.
Interposer: An interposer is an electrical interface routing between one connection to another for the purpose of rerouting the connection path or spreading it to a wider pitch. In 3D integration, the interposer material is either silicon, glass or organic laminate. Which material is used depends on the line and space requirements, cost, and performance requirements.
Monolithic 3D IC: Fabrication of a 3D IC that begins with a base wafer onto which additional layers of crystallized silicon and metalized layers are added using traditional fab equipment. The vertical interconnects are formed between layers rather than chips, using vias in the nanometer rather than the micron range.
PoP: Package on Package combines vertically discrete logic and memory ball grid array (BGA) packages. Two or more packages are stacked and interconnected with a standard interface to route signals between them. Wire bond, flip chip, through mold via (TMV), and bond via array (BVA), are all different interfaces that have been used to form the interconnect.
SiP: Also known as a multichip module (MCM), System-in-Package (SiP) refers to a number of integrated circuits enclosed in a single module that performs all or most of the functions of an electronic system. Traditionally dies in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal circuit board.
I²SiP: Recently coined by Fraunhofer IZM-ASSID – this refers to an integrated active multifunctional packaged device that provides not only TSV and multilayer redistribution (RDL) on both sides, but also features integrated passives; embedded actives and/or MEMS; integrated optical & electrical interconnects, and active cooling.
TSV: Through Silicon Vias are vertical electrical connections that pass completely through a silicon interposer or die filled with copper, tungsten or polysilicon. They directly interconnect circuitry on different dies, are very short (~ 50/100 um today) and enable high bandwidth, as well as very low latency between dies at extremely lower, interconnect power dissipation.
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