Ladies and Gentlemen of the semiconductor industry, we have a new acronym to add to 3D integration lexicon and its name is 3D SoC (aka: 3D system on a chip, or 3D system partitioning, or mixed node integration – take your pick). Whatever the moniker, it looks like THIS is going to be the one to remember most, as its likely to finally provide the technology/cost advantage that makes 3D ICs worth all the effort. We hope.

3D SOC was all the buzz at this year’s IMAPS International Device Packaging Conference (IMAPS DPC 2014), which took place March 11-13, 2014, at its traditional location at Fort McDowell Resort and Casino in Fountain Hills, AZ. In his keynote talk, “Die Stacking is Happening in Mainstream Computing,” Bryan Black, AMD, explained how 3D SoC partitioning works and its advantages. Black gave a similar talk at the 3D ASIP 2013 in December, when he first announced AMDs readiness with its high bandwidth memory (HBM) on logic technology. This time, he went a little deeper into detail about how partitioning works.

As always, cost is the primary motivation. Improvement in cost per transistor is why the industry adopts new process nodes, noted Black. However, as process complexity increases and mask count goes up, yield is dropping and cost is going up instead of down. And the disparate technologies required for today’s computing are not compatible with logic process nodes. “You give up performance when you try to combine everything on one die design,” explained Black. “However if you partition traditional SOC into special process nodes implementations you allow things to scale at a preferred pace.”

Black explained that by breaking up the SOC design into specific functions such as graphics node, cache node, CPU node, analog node, you can manufacture each technology in its optimal node instead of doing everything in the same node, based on the most complex node required by a particular function. 3D IC processes enable the stacking of these disparate technology nodes either in 2.5D configurations on an interposer, or in a 3D IC stack. This is, says Black, the path to improved performance, area and cost of each functionality.

Figure 1 shows AMD’s new HBM solution in both 2.5D and 3D IC configurations. It is a 4 die stack of DRAM on a logic die. Black said die stacking improves the proximity of DRAM to compute. Dense and fine-pitch interconnects enable simple low power interfaces as well as fine-grain power control of the DRAM. How does the GPU not heat up the DRAM? Built-in thermal control. “We made sure the DRAM is highly thermally conductive and pushes the heat right through,” explained Black. “It has the best cooling solution in the world sitting right on top of it.”  Black predicts that AMD’s HBM stacked DRAM will bring die stacking into mainstream computing market segments.

Figure 1. Examples of AMD’s HBM and Logic dies stacking configurations.

The question is, does 3D SoC really cost less than 2D SoC? According to a new online cost estimator tool developed by Ziptronix, it does. The company, known for its patented room-temperature wafer-to-wafer and die-to-wafer bonding processes, developed this tool to demonstrate the cost savings possible by building a mixed-node SoC in 3D using Ziptronix DBI® wafer-to-wafer bonding technology instead of using single node conventional 2D SoC technology. Rick McLellen, director of business development at Ziptronix, explained that with DBI, which stands for direct bond interconnect, it is possible to bond mixed-node wafers into stacks, reducing the overall area required to achieve the same functionality as complex large die 2D SoCs. The resulting chips are smaller in size, which increases wafer yield. An added bonus with DBI, is that two wafers can be bonded face-to-face without TSVs, or multiple wafers can be bonded back to front with TSVs. DBI also reduces the need for high aspect ratio (HAR) through silicon vias (TSVs), explained McLellen, as the interconnect is formed as part of the Cu-to-Cu bond. Skeptical? Take the tool for a spin here. The only inputs required for this estimator are CMOS wafer cost and yield for the single node 2D SoC and the two bonded process nodes; die sizes of the respective 2D and 3D SoCs; and post-bond fabrication and bumping cost.

While 3D SoC isn’t exactly a new concept – imec has had it on its technology roadmap for years, calling it the Holy Grail of 3D ICs – it is fairly new to the discussion of what’s going to (finally) drive volume manufacturing of 3D ICs. It’s just that the industry expected 3D ICs would happen long before 3D SoC was feasible.  Now that the need is here, could this be the big break we’ve all been waiting for? Even Black said AMD expected to ship its DRAM in 2005, but the world wasn’t ready for it. Could 3D ICs  now be damaging the adoption of a new node, just as advancements in wafer level packaging pushed out the adoption of 3D ICs? That would be an ironic turn of events. ~ F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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