Last week, I posted an executive summary of this year’s European 3D Summit, touching on the highlights and general takeaways based on the closing remarks I delivered at this year’s well-attended event, which took place January 23-25, 2017 at Minatec Campus in Grenoble. In this post, we’ll take a deeper dive into some of the edgier technologies in development that were presented, and what is driving them.

In his keynote talk, Qualcomm’s Mustafa Badaroglu looked ahead 15 years at the challenges we will be facing in computing and how they can be addressed using emerging 3D system-on-chip very large scale integration (3D SoC VLSI) approaches. He defined 3D SoC VLSI as: “Fab-driven integration technologies that allow functions to be synthesized and integrated into all three physical dimensions monolithically in the same way as conventional very large scale integration circuits.”  By “monolithically”, he’s referring to sequential 3D processes such as those implemented by Leti in its CoolCube technology; or by using direct bonding technologies, such as Invensas’ DBI™, which is used by Tezzaron Semiconductor in its 3D stacked devices. The advantages of each are illustrated in the slides below.

Figure 1: Wafer-level sequential integration. (Image courtesy of Qualcomm)

Figure 2: Wafer-to-wafer direct bonding. (Image courtesy of Qualcomm)

Badaroglu describes 3D SoC VLSI as “More than Moore scaling” because it can be used to integrate disparate technologies into a stack, as opposed conventional 2D SoC, scaling (aka “Moore’s law), which he says is facing fundamental challenges of heat, power, performance, complexity, and cost in 10nm and beyond.

Like with most 3D technologies, data requirements of mobile computing and the internet of things is the main driver for 3D SoC VLSI, and specifically Cloud and Edge computing. He differentiates the two as follows:

  • Big Data and abundant computing power are pushing computing to the Cloud
  • Instant Data generated by sensors and users are pushing computing to the Edge

Badaroglu wrapped up his talk discussing the challenges 3D SoC VLSI face with regard to electronic design automation (EDA), noting that EDA availability and system partitioning seem to be a challenge as opposed to the technology itself. Ultimately, though, he says 3D SoC VLSI can provide significant power/performance improvements over 2D SoC, and there is still room to improve if proper EDA solutions are supported.

Si Photonics

For several years, we’ve been hearing that integrating Si photonics into systems-in-package (SiP) would be a good approach to addressing the data bandwidth issue. In his presentation, ASE Group’s Jihan Chen noted that the high data rate demand is driving the need for Si photonics technology, due to its lower power, long distance, and lower bandwidth cost. Specifically, he says Silicon photonics is required to enable 400G SMF fiber optics for megascale data center applications. He went on to explain how embedded optics can be used to solve Ethernet switch data bandwidth issues.

Figure 3: Schematic of multi-chip electronics + photonics integration using fan-out SiP approach. (Image courtesy of ASE)

One of the challenges with using Si photonics has always been how to integrate it with electronics to get the high-speed optical signal off the package. Chen explained a multi-chip integration approach using chip-on-chip (CoC) in a fan-out SiP that supports photonics die and electronics die integration to create an optical engine. The short RDL signal path of this fan-out package suits the high-speed optics signal. The CMOS die is stacked on the photonics die using through silicon vias (TSVs) to enable better performance. Vertical/edge coupling for fiber optics is supported. This optical engine, which has demonstrated good Si performance and reliability, relies on the type of mature post-fab and wafer-level hybrid assembly processes, for which ASE has become known.  Chen expects that optical engine and Ethernet switch IC integration will become mainstream in the next few years.

Figure 3: VCSEL based optics co-packaged with microelectronics. (image courtesy of IBM Bromont)

Alexander Janta-Polczynski, of IBM Bromont, shared the company’s vision for automated high throughput assembly processes for photonic packaging. In comparison with current manual low-volume approaches that rely on active alignment, custom designs, and forming one connection at a time, an automated, high volume approach uses self-alignment, a standard design, and the ability to form multiple connections simultaneously.

IBM is leveraging its microelectronic packaging infrastructure and know-how to lower packaging cost and increase the scalability of Si photonics packaging. By taking a typical multichip module (MCM) with integrated optics and applying it to 2.5D and 3D package configurations, Janta-Polczynski demonstrated a single mode, multi-channel array photonic interconnect assembly using self-alignment and high throughput microelectronic tools.

3D SoC VLSI and Si photonics are great examples of why the quest for development of next-generation 3D integration technologies will continue as part the heterogeneous roadmap. ~ FvT

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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