Latest Posts
3D Systems-on-Chip: Clever Circuit Partitioning To Extend Moore’s Law
In recent years, the technology of 3D integration has evolved into an economically interesting road. In particular, the technology is...
The Edge of 3D: 3D SoC VLSI and Si Photonics
Last week, I posted an executive summary of this year’s European 3D Summit, touching on the highlights and general takeaways...
Xilinx Ultrascale+: 3D on Steroids
Ever since 3D transistors (aka FinFETS or Intel’s Tri Gate) 3D NAND, and monolithic 3D IC processes joined the family...
3D By Design: A Blog By and For the 3D Design Community
Earlier this year, I published an open letter to chip and system-level designers regarding 3D integration, suggesting they consider 3D...
SEMICON West 2014: Are 3D ICs Getting the Squeeze?
With the continued innovations in packaging technologies and 2.5D interposers pushing 3D ICs further out from one end, and 16/14nm...
Having the Courage to Design in 3D TSVs
I don’t know why it still surprises me to read conflicting reports on the progress of 3D TSVs. But I...
Is the Road to 3D ICs Paved with 3D SOC?
Ladies and Gentlemen of the semiconductor industry, we have a new acronym to add to 3D integration lexicon and its...Getting the picture in 3D
When you’re totally immersed in any one topic, and therefore listen to nothing but presentations about novel processes, solutions, progress,...
