With the continued innovations in packaging technologies and 2.5D interposers pushing 3D ICs further out from one end, and 16/14nm nodes already qualified without TSVs, making us wait until 10nm, are 3D ICs suddenly getting the squeeze from both sides? That’s one theory I took away from all the conversations and presentations at this year’s SEMICON West 2014, which took place July 7-10, 2014 at the Moscone Center in San Francisco. Here’s what lead me to this theory.

It all started during the SEMI Press Conference, where spirits were high because of increased spending in semiconductor equipment due to fab upgrades. Jonathan Davis, Global VP for advocacy at SEMI, attributed this growth to upgrades in DRAM technology (read 3D DRAM), as well as advanced packaging, flip chip and wafer level packaging (WLP). “Next year is on track to be the second largest spending year ever, surpassed only by 2000,” he noted.

In a panel discussion during the press conference, talk turned to 2.5D and 3D as moderator Karen Savala, president, SEMI Americas, seeded the discussion by pointing out that delays in EUV lithography and the transition to 450mm wafers is raising the dialogue about the end of Moore’s Law to a new level. Scaling below 32nm has developed more slowly than previous nodes. We’re starting to ask if it makes economic sense to continue traditional scaling.

Rob Kappel of KLA Tencor ticked off cost, EUV not being ready, new materials and yield as the biggest manufacturing issues with the scaling approach. “Its extremely hard to yield these devices,” he explained. “If you have 1000 process steps and each yield at 99.5%, the yield at the end will be 0.” He also noted that these smaller nodes will be very application specific, and while scaling will continue to serve those applications, they will not be widely adopted or needed for most mainstream devices.

An Steegan, Senior VP of technology development at imec, said device scaling and system scaling enabled by 3D transistors (FinFETS), stacked nanowires, and adoption of 3D IC stacking at the chip level, as well as 3D SOC stacking offers cost performance benefits, and that quick enablement of that roadmap would be a plus. She says hybrid bonding is a key enabler of 3D SOC, and that equipment and material suppliers are working on that. Indeed, she sees converging roadmaps of with cost reduction of 3D IC and a move to 3D SOC device stacking, all enabled by hybrid bonding. At this point, I was feeling pretty good about the near future for 3D ICs.

Then I went to the SEMI/Gartner Market Symposium, where Sam Wang of Gartner offered his hypothesis of why 3D has yet to take off, despite no intrinsic process technology show stoppers for memory on logic. He says 3D IC is ahead of its time and that while technology enables new applications, it’s the market that ultimately drives technology. He said 3D IC doesn’t offer sufficient advantages of 2D to drive the existing market or to break into a new market sector with great growth rate. He believes that time will come after 14nm finFET production in 2016, because larger die deteriorate overall yield, and are therefore more likely to adopt 3D ICs as the technology node shrinks. Higher yield will be achieved if replaced by multiple smaller die using 3D ICs. (Think Xilinx Virtex family). Wang’s theory threw hot water on the idea of the advantages of stacking 28nm die for improved performance, vs. going to the next node.

On Tuesday, I attended the STS forum, and asked panelists, Doug Yu of TSMC, Ron Huemoeller, of Amkor, and Calvin Cheung, ASE if they agreed with Wang, or if they thought that 3D ICs would happen before 14nm FinFETS. All of these companies have moved into production with 2.5D interposer technologies, and are ready to move with 3D ICs when someone pulls the trigger. TSMC is positioning itself to handle whatever comes there way, whether its continued scaling, CoWoS process for 2.5D, or its own version of FOWLP dubbed InFO.

I wasn’t expecting the answer I got – which was that when it comes to using TSV in 3D ICs for logic applications, it may indeed even skip the 14nm and not be designed in until 10nm before it happens because of thermal issues, cost and yield. Hueomoeller, the most optimistic of the three, reminded me that 3D ICs are happening already in the memory space. “TSV integration from the memory perspective is here because the performance case has been made with the Hybrd Memory Cube (HMC),” he said. After the discussion, Sesh Ramaswami, of Applied Materials and Bill Chen, of ASE, took the time to explain further, that the reason for the node skip is due to the fact that 14nm is already qualified without TSV, and that to use them in large nodes (28nm, 20nm, 16nm, etc) would require back-qualifying these nodes. During his keynote at the 3D InCites Awards, AMD’s Bryan Black confirmed that.

Another fly in the ointment came from Gartner’s Bob Johnson, who said only a few high volume/high performance applications will justify the costs of a new SoC design at 20nm and beyond. So that leaves us with a fairly small window of 3D IC opportunity when it comes to logic devices, if we have to wait for 10nm to design in TSVs. Unless of course, we back qualify larger nodes to get the cost/performance benefit of TSVs. See why I’m confused?

So then I started asking questions, and the opinions are as diverse as the number of packaging technologies in the industry. Brian Sapp, who has been spearheading SEMATECHs 3Di program for the past few years, wasn’t as swayed by the concern that 28nm would need to be back-qualified to have TSVs put in. “3D integration is the way to go,” he said. “Stick with 28nm and stack it.” He’s not talking about 2.5D either. SEMATECH’s work has focused on true 3D IC, TSV scaling, wafer thickness scaling, and attention to die-to-die and wafer-to-wafer processes.

I talked about my theory during my annual briefing with Manish Ranjan, Ultratech. His take is that it’s a question of prioritizing R&D dollars. It’s his belief that in the front end, the focus will continue to be on scaling to 16nm and 14nm and working out the yield issues, rather than investing in TSVs. He explained that the performance benefits of 16 and 14nm mean longer battery life and better leakage control. People are willing to pay for that performance. He also had an explanation why 28nm will be a long node. “28-20nm doesn’t give you a big performance improvement. So R&D will be invested in smaller nodes. Additionally he said the move from 16nm to 14nm means you’re going from 2D transistors to 3D transistors, which takes even longer. “Packaging is becoming important, but not that important to compete with front-end scaling,” he noted.

Interestingly, Ranjan doesn’t thing the delay to 3D is necessarily a bad thing. He says advancements in flip chip and wafer level packaging will serve as a backbone for 3D, because it leverages the same equipment sets. “A delay again for 3D gives more time to ramp the infrastructure, which will bring the cost down at a later point,” he said. “Companies have to figure out when they want to jump into it. If Qualcomm goes 3D, everyone will do it.”

So while many news sources are reporting that 3D ICs have arrived in high volume, as much as I’d like to, I’m not buying it. What’s you’re take? Is 3D IC getting the squeeze? ~ F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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