Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel

Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel

All hell broke loose at the 3D Panel discussion at the 2014 IMAPS International Device Packaging Conference. Nobody was hurt, and nothing got thrown, mind you, but it’s clear that we’ve got some very different opinions regarding one of my  pet peeves – the ever-expanding and increasingly complex advanced packaging nomenclature.

Oh it started out innocently enough. The aim of the panel, titled, “What’s Driving the Next Technology Revolution in Packaging?” was to have industry leaders representing technology, equipment, and research tackle questions on what is driving the next technology revolution in packaging. The focus was not only on 2.5D and 3D ICs, but also fan-out wafer level packages. Jan Vardaman, TechSearch International, was the moderator, and she posed a prepared list of questions to the panel. Panelists included Sitaram Arkalgud, VP 3D technology at Invensas; John Dzarnoski, director of microelectronic packaging at Starkey Hearing Technologies; Ron Huemoeller, Sr. VP of Advanced 3DIC at Amkor; Ravi Mahajan, Sr. Principal Engineer, High Density Interconnect Pathfinding, Assembly Technology at Intel; and Bob Patti, CTO of Tezzaron Corporation.

Huemoeller led off the discussion noting that what is driving packaging technology is the notion that it is more about systemization of product technology and involves a combination of multiple technologies. He said he’s seeing this in various forms, and that “system-in-a-package” (SiP) is not a good identifier any more. System-level integration is closer. The other panels concurred. Dzarnoski said in his area of the market, medical electronics, it’s all about modularization and sensor integration. Patti noted that for Tezzaron, 1/3 to half of the products are sensor-related. “Performance and power go hand-in-hand,” he noted. “I/O power dominates the systems we work on.”

This sparked the initial discussion of how we define SiP. Opinions diverged. Arkalgud defined it as “all about wire bond” and packing a lot of chips into a package. It does not use 3D stacking or through silicon vias (TSVs). Essentially, he sees it as things that are put together with solder balls and wire bonding, is very inexpensive and works well.  Patti agreed, noting that 3D and 2.5D are not SiP in general. “They maybe part of an SiP, but what we can do with 2.5D and 3D far exceeds what we can do with SiP,” he said.

Vardaman disagreed, explaining that in Japan, 2.5D is the ultimate SiP. Huemoeller said in general, SiP refers to the wire-bonded variety, but that there is a new class of SiP that refers to system-level, electrically managed products that have integrated passives. Mahajan said that at Intel, as long at its done in a small module it’s an SiP. Dzarnoski said SiP is simply a stand-alone module containing memory, processor, and capacitors. At this point in the discussion, I was thinking how complicated terminology had become.  We put that topic to bed for the moment.

Talk turned to fan-out-wafer-level (FOWLP) technology. Vardaman asked the panel their thoughts on why it hasn’t been adopted more.  Dzarnoski explained that die are getting smaller and I/O is increasing. “When you can’t deal with that anymore, you need a FOWLP,” he said. Huemoeller noted that while FOWLP provides a really thin package suited to system-level integration, its limited to playing where larger packages sizes can be accommodated, and has opportunity in more rugged-type devices. His take was that a 3D version of it in a package-on-package (PoP) will be a challenge. Patti said that at 25µm FOWLP is “something we can use.” He called it the “poor man’s interposer”, explaining it doesn’t require through silicon vias (TSVS), and can be assembled using “possum mounting.” “It’s a cheap way of getting a lot more I/O into a very small die,” noted Patti.

On the topic of “what will be the next high volume manufacturing (HVM) application for 2.5D interposer technology other than FPGAs”, the responses were varied. Patti predicted logic with memory, because DDR4 is barely an improvement on DDR3. “We’re limited by physics,” he noted.  2.5D can significantly reduce power and increase performance. Mahajan agreed, noting “high bandwidth memory on logic is the right application for 3D.”

Arkalgud cast his vote for GPUs for high-performance server applications, because like Xilinx FPGA applications, they are not as cost sensitive as consumer applications. Huemoeller added to this, saying that 2.5D technologies from Amkor will come out in graphics products first, including high-end computing and graphics cards. “The first entry is to address is logic to memory bandwidth,” he said. “There’s a big issue with graphics. The power budget is consumed by the memory interface. That can be put on the interposer.” He added that in high-end graphics cards, SOC partitioning (3D SOC) offers a cost savings below 20nm that is driving a lot of customers to consider this option. He added that while mobile-centric applications are looking to 14nm devices to make them as small as possible, it may not be best for all the parts to be in the same SoC because it drives power.

“2.5D buys you a lot, with 90% energy savings and a supply chain that is easy to accept,” noted Patti. “There’s so much low-hanging fruit at 2.5D. There are only a few things that will force 3D. 3D is something that has to survive on its own. It won’t happen on cost perspective.” He’s even coined the term,“5.5D” in reference to assembling 3D devices on a 2.5D interposer. In the long term, Patti sees the interposer as the next circuit card.  There’s a trade-off, he explained. It’s more expensive to build the module, but the cost of NOT doing 2.5D is prohibitive at the system level because most of our applications are performance driven.”

It was at the mention of 5.5D, that Phil Garrou, who had been interjecting quietly from the audience, had clearly had enough of this acronym alphabet soup. “Ho Ming Tong used 2.5D as a joke!” he said, referring to a presentation the ASE executive had given back in 2009. “We weren’t ready for 3D; we didn’t have standardization of where the I/Os are. So he came out and said, ‘put it on silicon and call it 2.5D because we’re getting closer to 3D.’ This new nomenclature makes no sense! Everything is an interposer. A BGA is an interposer! Why not just call it a silicon BGA?” That launched a free-for-all as more attendees chimed in with other examples, like how ridiculous the term “middle-end-of-line” is. There is no middle end, just a middle. And with front-end-of-line and back-end-of-line, and then far-back-of-line… well you can just imagine where this all was headed.

I have to say I agree with Garrou. The 2.5D term has always annoyed me.  Who ever heard of half a dimension? Bryan Black, of AMD said as much in his keynote the next day. “2.5D and 3D are the same thing to me,” he noted. “They are both die stacking. You’re getting rid of metal and getting rid of communication overhead.”

So in retrospect, while many good points were made during the panel, what most will take away from it is the utter chaos of terminology we’ve created for the advanced packaging world as new technologies are added to the mix. As the function of semiconductor packaging moves out of the wings and onto the main semiconductor manufacturing stage, and the industry adopts an open ecosystem supply chain approach, it might be time to set some standards around nomenclature. Just saying…~ F.v.T.

  • Funny! and True! and we know the story of the six blind men and the elephant… I assume we do… They are all correct, but yet incomplete, ecause they view this “elephant” from their perspective. Great article Francoise.

    • Thanks, Rajiv! Of course the Happy Hour setting may have had something to do with the liveliness of the discussion! But seriously, it would be good to get some sort of agreement on terminology so we’re at least all talking the same language!

      • 6 blind men and 2.5D…
        1st Blind Man: 2.5D is BGA.
        2nd Blind Man: 2.5D is WLP,
        3rd Blind Man: 2.5D is MCM,
        4th Blind Man: 2.5D is SiP.
        5th Blind Man: 2.5D is SOC.
        6th Blind Man: 2.5D is 3D.
        … and count me as the “3rd Blind Man” to Phil’s 1st. 😉

        I suppose the reality is all-of-the-above depending upon the history of the product evolution from 2D. Lot’s of innovation on the horizon…

        • Ed! Welcome back to the conversation. Glad to see you here. Looking forward to more comments from you.

  • Rick McClellan

    Francoise. Excellent summary and many thanks again to the panel for the time and insight shared.

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  • Paul Silvestri

    Another interesting article Francoise! Thank you.

  • Sunil

    Always a pleasure to read your articles- Excellent summary/commentary of this event..I heard Jan did very well in keeping the conversation on track- Cost is driving the next evolution in Packaging – and its not overall system level cost. Component (either it is a SiP, MCM,MCP or XD) cost counts the least these days.

  • Terminology related to TSV, 2.5 or 3D, 5.5D…. is one of the key aspect standardized under SEMI umbrella. This is crucial when planning to manufacture products. Feel free to contribute by registering online and attending any meeting. Next meeting is planned on April 1st in San Jose, CA.

    • Bill Acito

      If not these names, which ones? 2.5D may not be “dimensionally” correct, but it is short, unique, and now well identified. What would you replace it with? I am sorry I missed this panel… 🙂

  • Gretchen

    Thanks for the interesting read, Francoise. Sounds like one LIVELY panel! Wish I’d been there — fuzzy nomenclature makes me crazy.

  • Dr. John Miranda

    The term “System in Package (SiP)” refers to a philosophy in as much as it is a descriptor for small, high performance, and highly integrated semiconductor packages. The SiP philosophy in practice is not bound to any one type of application, assembly method, equipment set, or by the complexity of each of its integrated parts.

    SiP as an advanced packaging design philosophy, to its furthest extent, employs the latest technological advancements of the time (to come) – SiP’s contributions are at the ‘bleeding edge’ and in its wake are novel SiP solutions that go on to be exploited by industry Followers. This is to say that SiP oriented companies and their employed practitioners are themselves market Leaders. In detail, SiP concerns itself with high performance, size reduction, component integration, systems integration (SoC), DFx (mfg., test, etc.), power, reliability, cost control, efficient assembly & test processes, Quality – including many other design concerns influencing ROI (from Phase 0 to End-of-Life). Please don’t be blinded by the def. on Wikipedia.

    Today, the ‘internet of things’ and ‘wearables’ demands small highly integrated systems solutions that are densely packed with sensors, controllers, RF, actuators, optics, and memory – all of which can be interconnected using advanced packaging technologies. In 2014 these emerging products are the beneficiaries of ‘System in Package’ innovations, and just the fact that we can densely integrate to this degree is a testament to the progressions of SiP.
    To cast off “SiP” as just another outdated term and to simply replace it with new jargon is a disservice to our semiconductor packaging industry, and virtually dismisses SiP’s history and those ever associated with it. Today, the term SiP transcends even that one company that could proudly claim its very existence, but that contribution is now a valuable thing for everyone to embrace. Additionally, SiP should take it’s rightful place in our semicon packaging history & future, and in our college textbooks, and in your discussions about creating the next groundbreaking SiP solution or related enabling technology.

    J. Vardaman, R. Mahajan, and B. Black were true in their captured comments about SiP – I took a sigh of relief. One must be astute to separate true SiP innovation from Marketing’s attempts at differentiation with its unchecked creation of sometimes confusing jargon. All understand that companies must differentiate their products and services to generate revenue; but take note that confusing nomenclature and ambiguity may actually be viewed as good thing for their business acquisition efforts and attempts to justify the price of goods versus the competition. However, do we really want our industry’s customers to be confused and frustrated? Might we do better for our customers and the advanced packaging profession if we focus on invention and the true ‘value add’?

    Why do I care? I was a newly minted Ph.D. ME hired into the very first SiP group founded at Amkor Technology USA. My boss (now a CEO elsewhere) at the time coined the term “System in Package (SiP)” – he handpicked me for his team and I internalized his vision for SiP and what had to be delivered in order to be innovative, competitive, disruptive, and to create altogether new business categories. I applied the SiP philosophy to create among the first and new SiP packages for, Camera Modules before they were pervasive in emerging mobile phones, Smart Cards & Multi-media Cards (stacked memory) before their market adoption, Integrated RF components. Later in my career, I lead teams to create SiP true Wafer Level Cameras using SoC Imagers/TSV/WLO/BGA-on-Silicon, and Laser Based RGB Scanning MEMs Light Engines for pico projection. After 15 years its great that SiP is still a part of our vocabulary but I couldn’t sit back on this topic without an attempt to set the record straight about what SiP has always meant since its inception.

    • Hi John,
      Thank you for this insightful contribution! I appreciate that you took the time to educate me and our readers on the history of SiP, and what the true meaning is. It seems that by this definition, SiP could be considered the term for the overall architecture of heterogenous integration. Would that be a correct assumption? I don’t mean to imply that we should retire certain terms, but it would be helpful, I think, to all be clear on the definitions of each term we introduce. For example, imec and ITRS use 3D SIC (3D stacked ICs) in reference to 3D stacked die using TSVS; while reserving the term 3D IC to refer to monolithic 3D ICs. But much of the industry uses 3D IC as a catch-all term for stacking with TSVs and no interposer. What is your take on that?

  • Thanks for the great summary of the panel.
    I believe that the real issue is is not the terminology but the lack of standardization throughout the industry.
    When you mention WLP, for example, each Subcon has his own idea and variation of Wafer Level Packaging, and there is zero collaboration between them and they see their own version for Advanced Packaging as a competitive advantage. The disagreement among the panel members is a good representation of the state of the industry and the lack of standardization of Advanced Package technologies, process flow, material, equipment, etc.

    Coming from the Assembly Equipment perspective, you can realize that this lack of standardization poses a HUGE challenge for any supplier to the Assembly ecosystem. You can bet on one of the technologies and work with a specific Subcon on development of an Advanced Packaging solution (their unique version of it) with no visibility on whether you are betting on the right horse, so this takes out of the race many companies that can not afford spreading themselves so thin and work on multiple solutions for the “same” technology with multiple Subcons (supposedly the same, but it is hard to leverage the success with one Subcon and apply it to another). Add to the mix the fact that the entire Business Model for Semiconductor Assembly is also changing, and now it is not quite clear how much will the Foundries get into Advanced Packaging and Wafer Level Packaging, and how will this impact the relationship between Foundries and Assembly Subcons.

  • Dr. John Miranda

    I too view ‘SiP’ as the modernization & advancement to the predecessor MCM – which expands the packaging solution set beyond only ICs packages. Oversimplifying, an ‘MCM is a SiP but not all SiPs are MCMs’ that is because the SiP concept opened the door to integrating much more technology into a package, that includes onto a die(s) (digital, sensors, imagers, analog, wafer/on-die optics, RF, MEMs, lasers, LEDs, etc.). SiP also precipitated ‘smart’ and ‘sensing’ devices among other notable differentiators. Considering this, one can see that ‘heterogeneous integration’ seems to apply an incompatible constraint.

    Clearly, I am not suggesting the creation of yet another term or definition. I am only sharing the nuances of SiP to prevent just that (per the articles captured comments). Before suggesting new nomenclature for the industry we must master existing nomenclature, which requires us to take off our ‘market segment blinders’ to assess the industry’s changing landscape.

    I offered that SiP is a descriptor under which many other packaging solutions can be categorized alongside IC only packages (e.g., die/package stacking); which also benefits a formal place that captures the ‘history of device evolution’ and continued advancement of minimalized cameras, MEMs packages (acoustics, sensing, fluidics), and other highly integrated packages – much like your suggestion for an industry catch all term. It is under these meaningful, industry accepted definitions that we can bin any variances – whether useful or not. The market and its ecosystem players will either adopt or put an end to some nomenclatures (no need to lose sleep); whatever is adopted will be useful to the industry, enable collaboration, contribute to efficiency, and support transparent meaningful business transaction – that’s the point of it all.

    Thanks for reminding me about ITRS, I reviewed its white paper and I am very glad that we are not far apart about what SiP is today and how it will continue on. Has the concept of SiP grown over the years? most definitely, but that is what happens when innovative engineers grab onto a novel concept & enabling technologies and run with it.

    { I’m a big fan of 3DInCites. Francoise thanks for your kind feedback and keep up your great contributions. }

    • John –
      Thank you for your kind words. We’ve been talking a lot about packaging nomenclature this week during my travels through Europe. I agree with your statement: “Before suggesting new nomenclature for the industry we must master existing nomenclature, which requires us to take off our ‘market segment blinders’ to assess the industry’s changing landscape.”
      I would add that we also must agree on existing nomenclature! For instance, the ITRS, imec and SEMI refer to 3D stacked ICs (3D SIC) when many just use 3D IC as a catch all.

  • FvT: nice write up on nomenclature and I did not see the offending personal attack comments but these should not be tolerated

    Let me throw another confusion on acronyms and when context around the acronym’s usage is required to understand what is being discussed; yes similar to the ‘to’, ‘too’ and ‘two’. We have two SiP and SIP….System in Package and Silicon IP. Since I have worked on both sides of this debate, ‘SiP’ probably could claim ‘rights’ to first usage. But, let me kick up some dust….

    I would rather see ‘SiP’ changed to ‘SLP’, System Level Packaging: retire SiP. Many readers have stated that we are starting to add many other components to support More than Moore technologies to increase the functionality and performance while reducing power, cost, weight and form factor. SLP would be the global banner for any of the above mentioned packaging solutions….

    R.I.P. SiP?