Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel

Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel

All hell broke loose at the 3D Panel discussion at the 2014 IMAPS International Device Packaging Conference. Nobody was hurt, and nothing got thrown, mind you, but it’s clear that we’ve got some very different opinions regarding one of my  pet peeves – the ever-expanding and increasingly complex advanced packaging nomenclature.

Oh it started out innocently enough. The aim of the panel, titled, “What’s Driving the Next Technology Revolution in Packaging?” was to have industry leaders representing technology, equipment, and research tackle questions on what is driving the next technology revolution in packaging. The focus was not only on 2.5D and 3D ICs, but also fan-out wafer level packages. Jan Vardaman, TechSearch International, was the moderator, and she posed a prepared list of questions to the panel. Panelists included Sitaram Arkalgud, VP 3D technology at Invensas; John Dzarnoski, director of microelectronic packaging at Starkey Hearing Technologies; Ron Huemoeller, Sr. VP of Advanced 3DIC at Amkor; Ravi Mahajan, Sr. Principal Engineer, High Density Interconnect Pathfinding, Assembly Technology at Intel; and Bob Patti, CTO of Tezzaron Corporation.

Huemoeller led off the discussion noting that what is driving packaging technology is the notion that it is more about systemization of product technology and involves a combination of multiple technologies. He said he’s seeing this in various forms, and that “system-in-a-package” (SiP) is not a good identifier any more. System-level integration is closer. The other panels concurred. Dzarnoski said in his area of the market, medical electronics, it’s all about modularization and sensor integration. Patti noted that for Tezzaron, 1/3 to half of the products are sensor-related. “Performance and power go hand-in-hand,” he noted. “I/O power dominates the systems we work on.”

This sparked the initial discussion of how we define SiP. Opinions diverged. Arkalgud defined it as “all about wire bond” and packing a lot of chips into a package. It does not use 3D stacking or through silicon vias (TSVs). Essentially, he sees it as things that are put together with solder balls and wire bonding, is very inexpensive and works well.  Patti agreed, noting that 3D and 2.5D are not SiP in general. “They maybe part of an SiP, but what we can do with 2.5D and 3D far exceeds what we can do with SiP,” he said.

Vardaman disagreed, explaining that in Japan, 2.5D is the ultimate SiP. Huemoeller said in general, SiP refers to the wire-bonded variety, but that there is a new class of SiP that refers to system-level, electrically managed products that have integrated passives. Mahajan said that at Intel, as long at its done in a small module it’s an SiP. Dzarnoski said SiP is simply a stand-alone module containing memory, processor, and capacitors. At this point in the discussion, I was thinking how complicated terminology had become.  We put that topic to bed for the moment.

Talk turned to fan-out-wafer-level (FOWLP) technology. Vardaman asked the panel their thoughts on why it hasn’t been adopted more.  Dzarnoski explained that die are getting smaller and I/O is increasing. “When you can’t deal with that anymore, you need a FOWLP,” he said. Huemoeller noted that while FOWLP provides a really thin package suited to system-level integration, its limited to playing where larger packages sizes can be accommodated, and has opportunity in more rugged-type devices. His take was that a 3D version of it in a package-on-package (PoP) will be a challenge. Patti said that at 25µm FOWLP is “something we can use.” He called it the “poor man’s interposer”, explaining it doesn’t require through silicon vias (TSVS), and can be assembled using “possum mounting.” “It’s a cheap way of getting a lot more I/O into a very small die,” noted Patti.

On the topic of “what will be the next high volume manufacturing (HVM) application for 2.5D interposer technology other than FPGAs”, the responses were varied. Patti predicted logic with memory, because DDR4 is barely an improvement on DDR3. “We’re limited by physics,” he noted.  2.5D can significantly reduce power and increase performance. Mahajan agreed, noting “high bandwidth memory on logic is the right application for 3D.”

Arkalgud cast his vote for GPUs for high-performance server applications, because like Xilinx FPGA applications, they are not as cost sensitive as consumer applications. Huemoeller added to this, saying that 2.5D technologies from Amkor will come out in graphics products first, including high-end computing and graphics cards. “The first entry is to address is logic to memory bandwidth,” he said. “There’s a big issue with graphics. The power budget is consumed by the memory interface. That can be put on the interposer.” He added that in high-end graphics cards, SOC partitioning (3D SOC) offers a cost savings below 20nm that is driving a lot of customers to consider this option. He added that while mobile-centric applications are looking to 14nm devices to make them as small as possible, it may not be best for all the parts to be in the same SoC because it drives power.

“2.5D buys you a lot, with 90% energy savings and a supply chain that is easy to accept,” noted Patti. “There’s so much low-hanging fruit at 2.5D. There are only a few things that will force 3D. 3D is something that has to survive on its own. It won’t happen on cost perspective.” He’s even coined the term,“5.5D” in reference to assembling 3D devices on a 2.5D interposer. In the long term, Patti sees the interposer as the next circuit card.  There’s a trade-off, he explained. It’s more expensive to build the module, but the cost of NOT doing 2.5D is prohibitive at the system level because most of our applications are performance driven.”

It was at the mention of 5.5D, that Phil Garrou, who had been interjecting quietly from the audience, had clearly had enough of this acronym alphabet soup. “Ho Ming Tong used 2.5D as a joke!” he said, referring to a presentation the ASE executive had given back in 2009. “We weren’t ready for 3D; we didn’t have standardization of where the I/Os are. So he came out and said, ‘put it on silicon and call it 2.5D because we’re getting closer to 3D.’ This new nomenclature makes no sense! Everything is an interposer. A BGA is an interposer! Why not just call it a silicon BGA?” That launched a free-for-all as more attendees chimed in with other examples, like how ridiculous the term “middle-end-of-line” is. There is no middle end, just a middle. And with front-end-of-line and back-end-of-line, and then far-back-of-line… well you can just imagine where this all was headed.

I have to say I agree with Garrou. The 2.5D term has always annoyed me.  Who ever heard of half a dimension? Bryan Black, of AMD said as much in his keynote the next day. “2.5D and 3D are the same thing to me,” he noted. “They are both die stacking. You’re getting rid of metal and getting rid of communication overhead.”

So in retrospect, while many good points were made during the panel, what most will take away from it is the utter chaos of terminology we’ve created for the advanced packaging world as new technologies are added to the mix. As the function of semiconductor packaging moves out of the wings and onto the main semiconductor manufacturing stage, and the industry adopts an open ecosystem supply chain approach, it might be time to set some standards around nomenclature. Just saying…~ F.v.T.