SiP

IMAPS 2017 SiP Conference Takes on Sonoma

IMAPS 2017 SiP Conference Takes on Sonoma

California’s Wine Country attracts visitors from all over the world. They can enjoy the scenic countryside, historic places, golf courses, tennis courts, gambling and of course great wine and excellent food. How well can a highly technical conference compete with all these “distractions”? Please read about the sessions I attended and judge for yourself! The Inaugural Conference and Exhibitio... »

MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained

MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained

Multichip module (MCM),  system-in-package (SiP), system-on-chip (SoC), and heterogeneous integration are all important semiconductor packaging technologies. They deserve to have, at the very least, a book written about them. However, herein I would like to give these technologies very simple descriptions. if you don’t mind. MCM MCM integrates different chips and discrete components side-by-si... »

NXP and Nepes Create Value with their First FO PoP SiP for IoT

NXP and Nepes Create Value with their First FO PoP SiP for IoT

Advanced packaging is a key enabling technology that not only serves as packaging support but also offers more value and cost reduction to the final products. The advanced packaging industry with its 7% CAGR between 2016 and 2022 (in revenues)¹ is undoubtedly a dynamic sector where innovations play a key role. NXP’s SCM-i.MX6Q fan-out package-on-package system-in-package (FO PoP SiP) with boot ... »

Rudolph JetStep S Lithography System Advances Panel-based Advanced Packaging

Rudolph JetStep S Lithography System Advances Panel-based Advanced Packaging

Wilmington, Mass. (May 23, 2017)—Rudolph Technologies, Inc. (NYSE: RTEC) announced today that it has received an order for its JetStep S Lithography System for fan-out panel-based advanced packaging processes. The system, which will ship in June 2017 to an outsourced assembly and test (OSAT) facility based in Asia, will be used to produce system-in-package (SiP) products that combine sensor, pro... »

More-than-Moore 2.5D and 3D SiP Integration

More-than-Moore 2.5D and 3D SiP Integration

A new book on 2.5D and 3D integration, written by Riko Radojcic and published by Springer, will soon be available. The book addresses the current status of More-than-Moore system-in-package (SiP) technologies and explores the technical and business tradeoffs for deploying these options in high volume commercial IC products. We’re pleased to provide an excerpt of the preface: “There is a lot of... »

SiP Impact, Smartphone Market Saturation… What is the Future of Fan-in Packaging?

SiP Impact, Smartphone Market Saturation… What is the Future of Fan-in Packaging?

Fan-in packaging has been a successful and steadily growing platform for over a decade. However, fan-in packaging should face a challenging future, announces Yole Développement (Yole), the “More than Moore” market research and strategy consulting company. Indeed, despite unchanged market drivers, Fan-In packaging is showing an uncertain future with a slowing down smartphone market and the gro... »

Convergence on the “Big Five”: Focus on Laminate-based Advanced SiP

Part four in a five-part series While many industry experts have long predicted the demise of Moore’s law, it’s only in the past few months that it seems we have exhausted current CMOS scaling methods. While it’s likely that scaling approaches will resume in the future as new materials, processes, and tools are developed, the reality is that these solutions are still in the early stages of d... »

Executive Viewpoint: The New Advanced Packaging Landscape

Executive Viewpoint: The New Advanced Packaging Landscape

You might recall that a few year’s back (October 2013, to be precise), 3D InCites’ regular blogger, Paul Werbaneth, had the opportunity to interview Dongkai Shangguan, then CEO of the National Center for Advanced Packaging (NCAP) in Wuxi, China, which he helped found along with nine investors. They talked about lots of timely topics: the importance of industry-wide collaboration to bring down ... »

Moore’s Law Passes the Silicon Stress Test at SEMI ASMC 2016

Moore’s Law Passes the Silicon Stress Test at SEMI ASMC 2016

Stress Test, noun: “A test designed to assess how well a system functions when subjected to greater than normal amounts of stress or pressure.”  [Source: Oxford Dictionaries.] The 27th annual SEMI Advanced Semiconductor Manufacturing Conference was off to the races the week of 16 May 2016 in charming Saratoga Springs, NY, for a three-day meet of invited keynote talks, technical papers, poster... »

Convergence on the “Big Five”: Focus on MEMS Packaging

Convergence on the “Big Five”: Focus on MEMS Packaging

Part three of a five-part series In the first two parts of this series, we focused on low-cost flip chip and wafer-level chip scale packages (WLCSP), identifying them as two advanced packaging platforms we consider to be among the “Big Five.” It is our belief at Amkor that convergence into these five platforms is driven by the shift away from PCs and notebooks, toward mobile devices, wearables... »

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