Part four in a five-part series
While many industry experts have long predicted the demise of Moore’s law, it’s only in the past few months that it seems we have exhausted current CMOS scaling methods. While it’s likely that scaling approaches will resume in the future as new materials, processes, and tools are developed, the reality is that these solutions are still in the early stages of development, and will require years before they are fully realized. In the meantime, it’s up to advanced packaging technologies to propel us forward to support the requirements of five key market segments: mobility, Internet of Things (IoT), automotive, high-performance computing (HPC) and memory.
What is “The Big Five”?
At Amkor, we have identified “The Big Five” advanced packaging platforms that we believe will enable this to happen. The figure below lists the market segments and identifies which markets are served by one or more of these platforms. While wafer-based, advanced system-in-package (SiP) serves all market segments, the other four are key to providing solutions that increase performance and provide a higher value to cost ratio.
The first three installments of this series focused on key platforms that make up the building blocks. They include low-cost flip-chip, wafer-level chip-scale packages (WLCSP), and MEMS and sensor packaging. This fourth post and the final one (which will focus on wafer-based advanced SiP) will pull it all together, looking at system-level scaling approaches to integrating these building blocks into advanced SiP solutions. This post focuses on laminate-based advanced SiP.
Laminate-based Advanced SiP
Traditional laminate-based SiP solutions have been around for some time and have been manufactured by EMS providers with PCB assembly design rules and relaxed form factors. Advanced laminate-based SiP solutions, on the other hand, are more complex systems that are miniaturized using tighter and smaller OSAT-based assembly capabilities. Advanced laminate-based SIP solutions serve a higher end of the market. This is the case for 4G/LTE RF FEMs, which require the complex integration of filters, mixers, demodulators, amplifiers and discrete devices in a highly dense form factor with ultra-low interconnect parasitics.
Advanced SiP helps integrate disparate technologies, such as a small microprocessor with embedded memory, a sensing element such as a MEMS device or image sensor, RF die, and power management ICs in a very small form factor. It is not unusual to find various different interconnects like wirebond, flip-chip and WLCSP BGA along with surface mounted components in these systems.
What qualifies laminate-based advanced SiP as one of the Big Five packaging technologies? It fits the bill for new market growth areas, providing a great deal of value in terms of form factor and increased functionality at a cost point that accelerates product penetration in new and existing markets. For example, laminate-based SiP solutions can enable miniaturized cost-effective solutions in the consumer and industrial IoT space, as it helps integrate increased functionality and component counts in very small form factors.
Laminate-based advanced SiP achieves the lowest form factor at cost and performance points that address market needs in RF, storage, automotive, IoT, and power segments. Laminate-based SiP solutions are currently in production at Amkor. In addition, Amkor provides a core design kit that enables customers to do module and substrate design and also supports system modeling, characterization and full turnkey services to achieve the smallest form factors and fastest time to market.
While there is no single solution that works for every customer or application, having the Big Five in Amkor’s portfolio, enables system scaling solutions with increased performance and the highest value to cost ratio. ~ R. Alapati
The fifth installment in this series on “The Big Five” focuses on wafer-based advanced SiP.