MEPTEC Luncheons returned big to The Bay Area on Wednesday, May 25, 2016, with a new venue (SEMI HQ), a new joining of forces (IMAPS-MEPTEC-SEMI), a great turn-out (fully committed, capacity-wise, as they say in the restaurant biz), and an inspiring talk by Bill Chen, ASE Fellow and Senior Technical Advisor, ASE Group.

As devoted readers of 3D InCites / 3D+ know, we started this blog in 2014 to follow the many interesting threads that weave together to form the sturdy cloth of heterogeneous integration, and Bill’s talk, on “Innovations in Heterogeneous Integration and SiP,” was right in our wheelhouse.

After all, our mission statement reads: “3D+ is inspired by heterogeneous integration. Our guest bloggers focus their expertise in 3D, MEMS, and compound semiconductors to investigate how all these technologies are heterogeneously integrated into next-generation applications.”

Back then [2014] we made reference to my statement in 2009 that “I think heterogeneous integration is the way 3D IC manufacturing techniques are going to launch into the commercial mainstream … I’ve said this before, but when you step outside US-centric thinking and look to see what Japan and the EU are doing with 3D IC, it’s all about adding functional value, or introducing novel products, via heterogeneous integration. Don’t know why we don’t hear more about heterointegration from the home team sluggers.”

Bill Chen is truly a home team slugger, and when he says that “Our current Moore’s Law progress is insufficient for our industry,” you believe him.

And, paraphrasing Gordon Moore’s original words about the proliferation of electronics in our daily lives, when Bill says “System-in-package (SiP) through heterogeneous integration will bring about a proliferation of electronics,” you double-down.

According to the final version of the International Technology Roadmap for Semiconductors, the final release before its phoenix-rise this month as the IEEE-led International Roadmap for Devices and Systems (IRDS), heterogeneous integration is defined as comprising “separately manufactured components” combined in some way via the use of interposers, 3D stacking, FOWLP, SiP, etc.

Bill Chen ASEAs Bill said about the value of heterointegration, channeling Aristotle, “The whole is greater than the sum of the parts.”

Is wafer-level chip scale packaging ( WLCSP) the father of all advanced packaging technologies? Given the evidence presented by Chen, in which successive Apple iPhone generations achieved slimmer and slimmer profiles as they incorporated more and more WLCSP components, the answer is yes.

And, next, the world (according to Chen) will converge on WLCSP’s progeny, fan-out heterogeneous integration for SiP, to keep things moving forward in the way needed for system-level performance and functionality to continue to advance even as the basic silicon transistors themselves, fabricated in leading-edge process nodes, for example 16nm Fin FET, become somewhat more expensive commodities.

How do you create the future? Bill Chen believes it’ll be created by the applied efforts of dedicated engineers working on heterointegration.

Engineers like our readers.

We’re just getting started.

You can join those efforts by participating in upcoming discussions at the all-day IEEE CPMT Heterogeneous Integration Technology Roadmap Workshop next week, at ECTC 2016, on Tuesday 31 May 2016 in Las Vegas, and also at SEMICON West 2016, July 12 – 14, in San Francisco.

Thank you to MEPTEC for the luncheon, thank you to SEMI for hosting, thank you to IMAPS for being part of the team, and thank you to Karen Savala, president, SEMI Americas, for closing the luncheon with the words “I always feel the world is going to be OK when I hear from Bill Chen.”

Yes indeed.

From Santa Clara, CA, thanks for reading. ~PFW

Paul Werbaneth

Paul Werbaneth is a long-time Contributing Editor at 3D InCites. Since entering the semiconductor industry…

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