Heterogeneous integrated circuit (IC) packaging has made a full entrance into the high-performance computing arena. The target applications are broad, running the gamut from artificial intelligence (AI), deep learning, data center networking, supercomputers, and autonomous driving. In fact, a new generation of deep learning AI, leading central processing units (CPUs) for data center servers as wel... »
Plasma Dicing Advanced packaging is bringing with it new ways to separate die from the wafer. In the past, wafer dicing was traditionally carried out using conventional dicing “saw”. However, this method has limitations such as die chipping or cracking leading to lower device yields. Also, the width of the blade removes valuable “real estate” from the wafer. Newer techniques include laser ... »
EV Group (EVG), a leading supplier of wafer bonding and lithography equipment, today announced that it has partnered with Ningbo Semiconductor International Corporation (NSI), a specialty semiconductor foundry based in Ningbo, China, in the development of the industry’s first process technology platform for wafer-level heterogeneous integration of gallium arsenide (GaAs) on silicon for use in R... »
Remember when device node scaling was the semiconductor superstar, and advanced packaging was the back-up singer? At the 15th Annual IMAPS Device Packaging Conference, held March 5-7, 2019, in Fountain Hills, AZ, it became clear how rapidly that hierarchy has shifted. From the keynotes to the panel discussion, to the Global Business Council session, speakers portrayed heterogenous integration (HI)... »
The high cost of moving to the next semiconductor technology node is changing the role of packaging and assembly in the electronics industry. Heterogeneous integration has become the solution to achieve the economic advantages that were previously met with silicon scaling. TechSearch International’s new report describes these packaging options, including silicon interposers, fan-out-on-substrate... »
Automotive reliability is a pivotal concern for heterogeneous integration technologies, especially as emerging mission profiles for electric and autonomous vehicles push component lifetimes out by two to three times or more over standard testing regimes. There has been an increasing realization of the importance of chip-package interaction (CPI) as a source of reliability issues in semiconductor a... »
The Microelectronics Packaging and Test Engineering Council (MEPTEC) held its annual heterogeneous integration symposium at SEMI’s headquarters in Milpitas, CA on December 5, 2018. Many manufacturing and test, as well as electronic design automation (EDA) and IC design experts, got together to present and discuss how to integrate heterogeneous functions in advanced IC packages to better meet cus... »
The people have spoken! The results of last week’s poll are in, and it looks like the majority of those who participated think we should keep it simple. When it comes to heterogeneous integration nomenclature for package architectures, it should be 2D or 3D. The Back Story The term “2.5D” has been a topic of debate in the advanced packaging world ever since it was first added to the industry... »
Ok folks. It’s that time of year again. SEMICON West 2018 is upon us. By the time you read this – IF you get the time to read this – it’s almost curtain time. Everything that needs to be prepped is done, and if it’s not, it’s too bad, because the show will go on! It seems like every year, there’s more and more content to choose from. And you must choose because it’s pretty much... »
Festivities at ECTC 2018 kicked off May 29, 2018, with a full-day Heterogeneous Integration Roadmap (HIR) Workshop. This workshop was a continuation of an ongoing series that have been scheduled alongside major conferences around the globe so that as many people as possible can participate. We’ve been following the progress since the beginning. I caught up with Bill Chen, president of the IE... »
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