heterogeneous integration

IMAPS 2019: Stalled Scaling Begets AI Opportunities For Heterogeneous Integration

IMAPS 2019: Stalled Scaling Begets AI Opportunities For Heterogeneous Integration

Chiplets and 5G were a kind of buy-in to play at the IMAPS 2019 Symposium high-stakes table last week in Boston, MA, but it was heterogeneous integration that took many a pot during the three days of the symposium, particularly when IBM Research held the HI cards. The quick summary from IMAPS about attendance at the Symposium is that “Final registration figures proved that IMAPS 2019 was the in... »

Heterogeneous Integration Component Flavors SEMI ASMC 2019

Heterogeneous Integration Component Flavors SEMI ASMC 2019

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.” G. Moore, “Cramming more comp... »

Advanced Heterogeneous Packaging Solutions for High Performance Computing

Advanced Heterogeneous Packaging Solutions for High Performance Computing

Heterogeneous integrated circuit (IC) packaging has made a full entrance into the high-performance computing arena. The target applications are broad, running the gamut from artificial intelligence (AI), deep learning, data center networking, supercomputers, and autonomous driving. In fact, a new generation of deep learning AI, leading central processing units (CPUs) for data center servers as wel... »

IFTLE 408: Plasma Dicing ; Intel compares High-density Packaging for HI

IFTLE 408: Plasma Dicing ; Intel compares High-density Packaging for HI

Plasma Dicing Advanced packaging is bringing with it new ways to separate die from the wafer. In the past, wafer dicing was traditionally carried out using conventional dicing “saw”. However, this method has limitations such as die chipping or cracking leading to lower device yields. Also, the width of the blade removes valuable “real estate” from the wafer. Newer techniques include laser ... »

EV Group Partners with NSI to Enable First Wafer-level Heterogeneous Integration of GaAs on Silicon for RF Front-end Module Manufacturing

EV Group Partners with NSI to Enable First Wafer-level Heterogeneous Integration of GaAs on Silicon for RF Front-end Module Manufacturing

EV Group (EVG), a leading supplier of wafer bonding and lithography equipment, today announced that it has partnered with Ningbo Semiconductor International Corporation (NSI), a specialty semiconductor foundry based in Ningbo, China, in the development of the industry’s first process technology platform for wafer-level heterogeneous integration of gallium arsenide (GaAs) on silicon for use in R... »

Heterogenous Integration’s Star Rises at the 15th Annual IMAPS Device Packaging Conference

Heterogenous Integration’s Star Rises at the 15th Annual IMAPS Device Packaging Conference

Remember when device node scaling was the semiconductor superstar, and advanced packaging was the back-up singer? At the 15th Annual IMAPS Device Packaging Conference, held March 5-7, 2019, in Fountain Hills, AZ, it became clear how rapidly that hierarchy has shifted. From the keynotes to the panel discussion, to the Global Business Council session, speakers portrayed heterogenous integration (HI)... »

Heterogeneous Integration Drives New Package Developments

Heterogeneous Integration Drives New Package Developments

The high cost of moving to the next semiconductor technology node is changing the role of packaging and assembly in the electronics industry. Heterogeneous integration has become the solution to achieve the economic advantages that were previously met with silicon scaling. TechSearch International’s new report describes these packaging options, including silicon interposers, fan-out-on-substrate... »

Heterogeneous Integration Calls for Increased Materials Reliability

Heterogeneous Integration Calls for Increased Materials Reliability

Automotive reliability is a pivotal concern for heterogeneous integration technologies, especially as emerging mission profiles for electric and autonomous vehicles push component lifetimes out by two to three times or more over standard testing regimes. There has been an increasing realization of the importance of chip-package interaction (CPI) as a source of reliability issues in semiconductor a... »

Highlights From MEPTEC’s 2018 Heterogeneous Integration Symposium

Highlights From MEPTEC’s 2018 Heterogeneous Integration Symposium

The Microelectronics Packaging and Test Engineering Council (MEPTEC) held its annual heterogeneous integration symposium at SEMI’s headquarters in Milpitas, CA on December 5, 2018. Many manufacturing and test, as well as electronic design automation (EDA) and IC design experts, got together to present and discuss how to integrate heterogeneous functions in advanced IC packages to better meet cus... »

What Should Replace “2.5D” in the Heterogeneous Integration Nomenclature?

What Should Replace “2.5D” in the Heterogeneous Integration Nomenclature?

The people have spoken! The results of last week’s poll are in, and it looks like the majority of those who participated think we should keep it simple. When it comes to heterogeneous integration nomenclature for package architectures, it should be 2D or 3D. The Back Story The term “2.5D” has been a topic of debate in the advanced packaging world ever since it was first added to the industry... »

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