In last week’s coverage of the Known Good Die Symposium, I talked about the notion of shifting focus from Known Good Die to Probably Good Die. It got me to thinking how by simply changing vernacular that we use, we can alter perspective and thereby affect a complete paradigm shift in the way we do things.

For example, have you ever wondered why the term “advanced packaging” was coined to differentiate conventional pick-and-place, wire bonded package processes from advanced wafer level packaging? It always seemed to be a misnomer, since it wasn’t the packaging part (ie: package assembly, overmold, singulation, and final test) that was becoming more advanced, but the interconnect method itself. Perhaps if instead of adopting the term “wafer level packaging” the industry had gone with “wafer level interconnect” the value-add of advanced interconnect technologies like flip chip, redistribution layers, wafer bumping, copper pillars, and through silicon vias (TSVs) would have been realized sooner.

I’ve been thinking about this a lot lately, as I’ve noticed the emergence of a new space in the industry between the front-end and back-end (commonly referred to the middle-end) and a new term emerging to define it: Interconnectology.

The origin of Interconnectology
Scott Jewler, currently Sr. VP at Advanced Nanotechnology Solutions Incorporated and formerly president of Powertech Technology USA, lists his occupation on Linked in as “Interconnectologist” a term he coined himself because “packaging no longer accurately describes the field.”

At IWLPC, the Invensas booth sported a banner announcing “Interconnectology by Invensas.” CEO Simon McElrea explains, “The terms ‘packaging and back-end’ don’t exactly stir the heart. Packaging connotes a box. Back-end makes you think of a horse. Those words don’t describe what the people in this industry do. From the chip all the way to the board, everything has to be interconnected together. It’s not just about the packaging.”

“The term ‘wafer level packaging’ is giving way to “electronic interconnect” as it’s the interconnect technology that provides the value-add at the system level to packaging technologies,” notes Tim Olson, CEO of Deca Technologies. This is one reason why Deca Technologies went with the tagline “transforming electronic interconnect” rather than “transforming wafer-level packaging.”

Interconnectology and Interconnectologist Defined
In speaking further with Jewler and McElrea, its clear there are two ways to define interconnectology: from a technical perspective and from a business-level perspective.

Jewler talked about how historically, interconnect was a front-end fab term. Traditional packaging involved 3 things: protection, electrical connection and thermal management. Thanks to fab scaling and reduced pitch sizes, he says packaging is now more about pitch translation, and connecting scaled devices to PCBs that don’t scale. In Jewler’s opinion, the next-generation of ‘packaging’ needs to be redefined with the additional process step of ‘interconnect’ to address those middle-end-of-line processes that are neither front-end or back-end.

“A switch in terminology helps change perspective,” notes Jewler. Thus, the term “Interconnectology” better defines issues related to chip-to-chip interconnects, like signal integrity, and higher speeds. “Traditional packaging steps still remain,” he explained “but there’s a new area emerging that is the value-add and involves finer geometries that are integral to the functionality of the device.”

“This is a call to arms,” says McElrea. “The people who pioneered packaging are disappearing and getting out of the back-end. There’s more importance being given to the middle end. We need to be hiring and inspiring more people into this industry.” He defines interconnectologists as those who are applying a skill set to the middle-end that was learned as a packaging engineer. This knowledge base includes materials science, mechanical and electrical engineering applied to the wafer level.

To manufacture 2.5D and 3D devices requires more knowledge than putting vias into silicon and plating them, explains McElrea. While the core competency to do this comes from the wafer processing industry, that’s only a piece of it. It doesn’t mean you’ll end up with a working product. There needs to be an understanding of how to put it all together, considering reliability and thermal issues at the same time. “The job for interconnectologists begins with the TSV right up to the physical connector/module level,” says McElrea. “It’s more than just packaging. It requires sufficient wafer-level skills overlapping with packaging skills.”

So there you have it. A new term is born. If Ho Ming Tong of ASE can coin the term “2.5D packaging” and have it take off, I’m pretty sure we can be successful with establishing “Interconnectology” and “interconnectologist” as industry terms. Spread the word. ~ FvT

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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