3D Readiness Report Card

While other presenters for the 2013 3D ASIP session, “Evolution of 3D Technologies and Market Trends” took a more conventional approach to reporting the status of 3D integration, Jan Vardaman, TechSearch International gets the prize for originality and humor for playing the role of “professor” and delivering the 3D readiness report card, grading progress in the key challenge areas. Her approach provided a great framework for later presenters who had some “extra credit” projects to submit, in an effort to improve the grade awarded by “Professor Vardaman”.

To set the stage, rather than reiterate the drivers that we all know well, she declared the drivers are still the same, 3D integration is needed and important. She also reminded attendees that current alternatives to 3D are not stagnating. “People need to realize that there are products being made in other areas, and the cost (of 3D ICs) is relative to other packages that are seeing innovation and development,” she cautioned. (Examples that come to mind include eWLB, Invensas’ Bond Via Array (BVA), and various advanced package-on-package (PoP) technologies.) “We believe developments in PoP have pushed out logic and memory 3D stacks with TSV for mobile applications,” noted Vardaman.

She assured attendees that her report card was not meant to paint a negative picture of 3D, but to encourage us to keep going. “New architectures and new designs take a lot of time. Please be patient!” said Vardaman.

Design Tools
Grades in the design space spanned from “A” to “F”. SPICE simulators for large memory vendors lead the pack with an “A”; suppliers for 2.5D pulled off a “B” (what’s on hand is good enough); floorplanning needs more effort and gets a “C”; 3D IC is a system level design problem and also gets a “C”. Thermally aware design flunked the exam. “I haven’t found anything I’m happy with on a thermally aware design,” declared Vardaman. As a whole, EDA vendors got an “incomplete” for a lack of relationships with material suppliers and equipment vendors.

Vardaman gave micro-bump bonding and assembly for fine pitch a “C” due to the lack of a high speed, high accuracy bonder. For temporary bonding/debonding processes, the equipment manufactures got a “D” for low throughput, yield loss, and expensive tools. But materials manufactures – 15 companies in all that offer temporary bond/debond materials got a collective “F” for a whole laundry list of unsolved issues including voids, total thickness variation <1µm, viscosity, adhesive conformity, mechanical stability, CMP, thermal stability, outgassing, particles, room-temperature debond, and more. “See the teacher for grade changes if you’ve got solutions to these challenges,” admonished Vardaman.

vardamanhotspotThermal issues scored and “F” for lack of a solution o the hot-spot problem when stacking memory on logic. She explained that DRAM expects uniform temperature of device, but the Logic chip can generate hot spots caused by non-uniform duty cycle of module.

Overall cost got a “D”, with much finger-pointing to yield loss do to wafer breakage during the debond step.

Infrastructure has come a long way in a short time, as has test; each scoring a solid “B” from Vardaman. The supply chain issues are being resolved with a variety of models expected to co-exist and improvement in teamwork.  Test scored for probe card development. Reliability data is still “incomplete.”

Extra Credit Work

Temporary Bond/Debond
EV Group’s Markus Wimplinger reported in with the company’s ongoing efforts in raising the overall grade for temporary bond/debond. Why is it so tricky and difficult? Adhesive requirements have to satisfy a variety of environmental requirements. The company is working for 100% yield. Equipment needs increased throughput, and EVG is working to increase it from 25 to 45 wafers per hour. They’ve integrated inline metrology for quick pass fail decisions, and claim to have the fastest total thickness variation metrology system on the market with more accurate results and more useful data to assist in process optimization.

Cost Reduction
In an effort to raise the cost grade from a “D” to an “A”, Sitaram Arkalgud, Invensas, pointed out where the company has identified the greatest cost adders, and are making efforts to find solutions. For the past two years, the company has been working to build a 2.5D interposer test vehicle and recently completed a cost modeling exercise with Savansys Solutions. Efforts to reduce assembly costs are underway, and the company has identified a number of focus areas for cost reduction.

Invensas3DASIP copy

First, a reduction in interposer size drops cost considerably. However, explained Arkulgud, for some applications a larger interposer is needed. In that case, adding more value to the interposer can also contribute to cost savings. Capillary underfill is slow and expensive. Cheaper underfill options are currently under evaluation. Chip on substrate vs. chip on wafer has some impact on cost, with a chip-on-wafer approach being slightly less expensive.

Another big cost adder is thermocompression bonding. Invensas is looking at replacing Cu thermocompression with reflow to bring down the cost. Lastly, Arkalgud examined the concept of scaling in 3D stacking.  Historically, scaling (CMOS and package) has typically driven down cost, he reasoned. Why not scale 3D stacks in an effort to reduce cost? He looked at chip-to-chip interconnect scaling using smaller microbump pitches, and increasing device density by scaling TSVs and also by increasing the number of dies in a stack.

Ziptronix’ answer to costly Cu thermocompression bonding (CTC) is its proprietary direct bond interconnect (DBI®) technology. Paul Enquist, CTO Ziptronix, explained the cost and technology advantages. CTC is done one wafer at a time, and requires external pressure and high temperatures to create the bond.  DBI is a low temperature bond that is formed without external pressure at low temps. The final bond is done in a batch anneal process. Enquist provided the following table to demonstrate the cost difference. According to this, DBI has 4:1 cost advantage over CTC due to lower tool cost and faster cycle time.

DBIcostadvantage copy

DBI also offers a scaling advantage, because of a better misalignment tolerance than CTC. It also has higher bond energy because the bond doesn’t only form at the bond pad interconnect but from the overlapping oxide.  DBI can be done without needing expensive TSVs or interposers; which is why backside illuminated image sensors (BSI) were able to ramp to volume production so rapidly, said Enquist.

IME’s Surya Battachara also presented some cost saving approaches to 2.5D through silicon interposer (TSI) technologies and alternatives to thin wafer handling. He noted that most of the interposer cost is in back end of line processes (BEOL). The Singapore-based research institute has been looking for ways to eliminate the damascene step to avoid using costly stepper technologies. They are proposing a Cu polymer redistribution layer (RDL) for low-cost coarse-pitch multi-level wiring of wide I/O memory

Alternatives to Thin Wafer Handling
faStack copy
A bigger task is the thin wafer handling issue. Not only is temporary bond/debond an expensive step, it’s also the one most fraught with technical issues. If they haven’t been solved yet, its time to look to alternatives for thin wafer handling and eliminate the temporary bond/debond step altogether, noted Arkulgud. Invensas is exploring chip to wafer bonding using wafer-level compression molding, or carrier-less wafer stacking, such as with Tezzaron’s FaStack process.

compressiionmoldinvensas copyLike Invensas, IME is also in favor of compression molding as an alternative to temporary bond/debond. Battachara explained IME’s chip-to-wafer (C2W) carrier-less flow, in which the C2W bonding and underfill steps takes place on a full thickness wafer, followed by wafer level overmolding. The mold provides the added support during backside via reveal, passivation and BGA ball drop.

Dave Howard, TowerJazz Semiconductor, offered his company’s solution to thin wafer handling. TowerJazz is considered a “specialty foundry” that fabricates CMOS image sensors, mixed signal CMOS devices, MEMS, TSVs and 3D IC.  The company has adopted the Taiko method from Disco for thin wafer handling, which involves grinding the middle of the wafer and leaving a ring of thick silicon around the outside. This pulls the wafer flat and results in a rigid wafer that is ready for support-free processing. Howard said TowerJazz processes 200mm wafers in this manner, which reduces costs and increases reliability.

Taiko Process 3D Readiness

From these extra credit projects, it’s clear efforts are being made to improve the 3D readiness report card. And these were just some of the suggestions offered at 3D ASIP 2013. In my next post, we’ll look at a few more interposer solutions.  The story continues…. ~ F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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