GSA Silicon Summit: What’s next for the 2.5D/3D Ecosystem?

GSA Silicon Summit: What’s next for the 2.5D/3D Ecosystem?

Due to schedule conflicts, I was unable to attend this year’s Silicon Summit, which took place April 10, 2014 at the Computer History Museum, and featured a segment titled GSA Silicon Summit 2014: 2.5D/3D Ecosystem – What’s Next? Luckily, Rick McClellen, director of business development at Ziptronix briefed me on the event key takaways, which I’ve noted here and offered some of my own observations in response to these, based on what I’ve been hearing at various industry events and from visiting with companies.

I also reviewed the post of industry blogger, Paul McLellen, who did attend the session and wrote about it here on SemiWiki. His main lesson learned, which I completely agree is critical to commercialization of 3D, is that the (3D) system needs to be architected from the beginning for 3D to take advantage of it. McLellen also pointed out some other key comments, which were also consistent with what we’ve been hearing at various industry events, such as 3D ASIP 2013, the 3D TSV Summit, and IMAPS DPC.

First of all, it seems that once again, 3D SoC and partitioning of die to optimize process nodes was all the buzz. There seems to be a basic agreement that in volume production, 3D SoC can be manufactured at a similar cost to 2D SoC.

Brandon Wang of Cadence commented that testing a 3D SoC will not cost more than testing 2D because “simply folding over a larger die from planar to stacked does not add time and cost.” I’m not sure the 3D test community would agree with this completely, because while it might not cost more from a design tool cost perspective, partial stack testing definitely adds additional steps to 3D test, and therefore additional cost. However, while it may cost more to test, value is added because it avoids assembling bad parts, which could ultimately cost a company more in the yield loss. Cascade MicroTech and imec have developed an approach that they say will make 3D test cost-effective.

Riko Radojcic, of QUALCOMM, who participated in the 2.5D/3D ecosystem panel, put in a request to Cadence to create tools for testing 2.5D and 3D solutions. This surprised me to hear, since at the DATE 2014 3D Workshop, Brandon Wang (who also was a panelist at the Silicon Summit) presented Cadence design tool offerings on 2.5D and 3D, which included (according to Wang’s slides from the DATE Workshop):

• Full Spectrum Analysis Capability RC/ET DFT and ATPG for 3DIC;
• EPS/ETS/QRC Digital Analysis Tool Configuration
• Virtuoso™ Based Full Spice Simulation Capacity
• SiP/Sigrity™ based Extraction, SI, and PI System/Package Analysis Power DC Thermal Analysis.

McLellen also reported “there are clearly some short-term issues of who owns yield loss. But longer term is, who does the R&D? Perhaps a consortium (modeled on Sematech) is needed to drive a roadmap that is out 5 or more years and to avoid building a cool solution that nobody wants.” This one has me completely confused, and maybe I needed to be there to understand the context. Was the suggestion for an R&D consortium for test? It sounds very familiar to what is happening in the European research centers like imec, Fraunhofer and Leti. All of them have various 3D consortiums with industry partners to bring products to market and base R&D on products and processes that are actually manufacturable and marketable. And isn’t SEMATECH also already doing this in the US? And ITRI and IME in Asia? What am I missing here?

Another point of discussion was the thermal issue. Jan Vardaman challenged the panel, asking them if they believe thermal issues are not showstoppers to 3D IC solutions. Radojcic accepted the challenge and noted that QUALCOMM has solved the thermal issue. At IMAPS DPC, the speaker from QUALCOMM noted that the demand for through silicon stacking (TSS) in mobile phones is there, and thermal would not be a showstopper. He also said that the thermal issues with WLP still exist and it hasn’t stopped them from being used in smartphones. Additionally, researchers at Fraunhofer IWM and Leti are aggressively tackling the thermal issues. In his presentation at the 2014 DATE Workshop, Fraunhofer’s Frank Altmann did aknowledge that thermal could indeed be a showstopper for 3D ICs, but he also presented some encouraging data on work being done to manage this. Additionally, Leti has partnered with Docea Power to introduce a thermal modeling tool to do system-level exploration of thermal effects before the system is built.

Also on the topic of design, and with regard to the need for SOC design, McLellen  noted in his post, “there is no pathfinding tool for doing the exploration at the early stage, exploring “what if” analysis with thermal, transistors near TSVs, reliability and other issues. Nobody is creating such a tool either since it is unclear if there are more than a handful of customers that would ever use it.” Again, I would disagree that “nobody is creating such a tool” as I heard mention of such developments addressed at DATE 2014 in a number of presentations from research institutes as well as Cadence and Mentor Graphics.

In general, as I notice discrepancies in information from event to event, I think what we have here folks, is a “failure to communicate” between the design community and the process and manufacturing community. I suggests we mix it up a bit, and get more design guys attending process and manufacturing events, and vice versa. ~ F.v.T.