Are slow standardization and CAD-tool development hindering the progress of 3D IC design and integration? This was the topic of discussion during the Friday 3D Workshop at DATE 2014, which took place this year in Dresden, March 28, 2014. I was invited to moderate this panel discussion, which featured panelists from EDA suppliers, industry, and academia. We wanted to mix it up a bit and involve the attendees more, so the organizers and I decided to employ the use of an online quiz app, Kahoot.It, to poll the audience on these topics as part of the panel to spark discussion. (Thank you, Bjorn B. Larsen, of NTNU for the great idea!) The panelists were Mustafa Badaroglu, Qualcomm Technologies, Belgium; Makoto Nagata, Kobe University, Japan; Jürgen Schloeffel, Mentor Graphics, Germany; and Brandon Wang, Cadence Design Systems, US.

Badaroglu lead things off by noting what standards we have in place today including: 3D standards for Wide I/O JEDEC memory interconnect; standards for 2.5D and 3D Test (IEEE P1838); foundry; reference design flows; Si2 standards for 2.5D and 3D exchange formats in design flow; and SEMI process standards for CMP, alignment markers, storage and transport, total thickness variation (TTV) measurements; metrology and microbump processes.

Schloeffel talked about progress with various design-for-test standards from Mentor’s perspective. He pointed out that the IEEE 1149.1 is state-of-the-art for boundary scan architecture, has been in place for decades, and is supported by all major EDA companies. IEEE P1838 test access architecture for 3D stacked ICs (3D SIC) is in its early phase and being worked on. Lastly, he noted that IEEE P1687 (IJTAG) for access and control of embedded instrumentation within semiconductors is very solid, and close to completion. “The second ballot round has started, and P1687 is in good shape,” he said. “We expect the standard to be approved this year.”

According to the results of the poll, which posed 3 statements and asked if the attendees agreed or disagreed to them, the majority of attendees agreed that the establishment of standards is crucial to high volume manufacturing of 3D ICs. The majority also felt that progress is being made, but that there is fragmentation among standards bodies and more collaboration is needed to address this.

In the discussion that followed the poll, Nagato noted that the locations of microbumps need to be standardized for HVM targets such as memory-memory stacking or memory-logic stacking, as there will be multiple chip suppliers involved. “More opportunities of prototyping 3D integrated systems will teach us real things and lead the progress of standardization as well,” he said.

Badaroglu added that we need standard taxonomy definitions for TSVs, backside, RDL, microbump, and stacking. He would also like to see a standard format for data/constraints between IP/IC providers, design, foundry, and OSATs to provide better manufacturing co-integration. Other items on his wish list include a unified PDK from OSAT to foundry, and standard formats that would enable design for easy thermo-mechanical simulation.

Schloeffel noted that establishing standards is important but not crucial. Standards help, but the market is not big enough to force standards today. Development of a new standard is a time consuming process. The industry will not wait for completion before evolving in HVM, he said.

The second audience poll focused on EDA tool readiness. While there was a 2:1 agreement vs. disagreement to the statement “available EDA tools are sufficient to achieve 3D designs”, the majority of those polled indicated that the availability of EDA tools would accelerate research and development of 3D processes, and disagreed with the statement “3D specific EDA tools are not important until 3D ICs are in volume manufacturing.” The verdict of whether or not EDA vendors should bear the cost of EDA tool development was split almost down the middle. I think some of these responses surprised the panelists.

In Nagata’s opinion, prototyping 3D IC chips can and should be accomplished with existing EDA tools for 2D design. “We do not want to wait for sophisticate 3D tools,” he noted. He said a design environment of 3D chip stack is ready, and demonstrated his point with silicon examples (Figure 1). He also pointed out that 3D EDA tools need HVM applications of 3D IC chips before getting really developed and going into penetration.

3D Standards
Figure 1: 3D TSV chip stack demonstrator featuring 4096b Wide I/O at 100 GB/s (figure courtesy of Makoto Nagata, Kobe University, Kobe, Japan)

Badaroglu noted that EDA tools should serve three functions. They should enable pre-design decisions, they should have sign-off with good models that alert the designer what to do, and that they should be standard to enable easy sharing between IP/Chip providers, design, OSATS and foundries.

Schloeffel highlighted Mentor Graphics work in design-for-test (DfT) 3D test, which is in used today for external DRAM. Additionally, Mentor solutions are included in TSMC’s 3D IC reference flow. The company bases its approach on “plug-and-play principles.” IJTAG is used to enable flexibility for changing requirements. DFT work is minimized at the 3D package level.

One example of Cadence offerings. (Image courtesy of Brandon Wang, Cadence) 

On his part, Brandon Wang took the opportunity to point out that Cadence already has as a 3D IC integrated solution. “Cadence has been working with ecosystem partners since 2007 on 3DIC and as a result has 9 test chips completed and 1 production chip done,” he said, adding that several projects are ongoing, one expected to tape out next quarter. He also pointed out that there are dedicated 3D features in tools that are already in use.

Jochin Reisinger, of Infineon, was not convinced that we have what we need to go forward. “We need design tools for thermal modeling so that design rules can be established. We are currently at zero with this, and have to do all kinds of re-spins to get it right,” he said, which adds to the cost of 3D integration. It seemed like the discussion was just getting started when it was time to break for lunch. I’m also quite certain that as I was moderator, I did not capture all of the discussion here. So I invite the panelists and readers to continue it here. Do you agree or disagree with the following statements? On Standards:

  • The establishment of standards are crucial to HVM for 3D ICs.
  • Progress has been made in developing standards in critical areas for the advancement of 3D IC design and integration.
  • There is fragmentation among standards bodies working to establish 3D standards, and more collaboration is needed to address this.

On EDA Tools:

  • Available EDA tools are sufficient to achieve 3D designs.
  • The availability of EDA tools would accelerate research and development of 3D processes.
  • 3D specific EDA tools are not important until 3D ICs are in volume manufacturing.
  • EDA vendors should bear the cost of EDA tool development.

I invite you to share your comments below. (If this is the first time you comment on 3D InCites, note that they will not appear immediately as they need to be approved by the administrator – me – and I promise to respond quickly!) ~ F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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