DesignCon 2016: Where the Chip meets the Board and Great Ideas Come to Life

DesignCon 2016: Where the Chip meets the Board and Great Ideas Come to Life

DesignCon 2016 at the Santa Clara Convention Center gave football fans among us an opportunity to watch the preparation work for Super Bowl 50. Right across the street from the Convention Center is Levi Stadium, where on Sunday, February 7, this year’s champion will be crowned. Impressive, but let’s not digress and focus on DesignCon.

drone

Figure 1: Intelinair flight controller for stable drone flight.

For me, in my role as business developer for innovative products, the highlight of DesignCon 2016 was Tuesday’s brief, but very powerful keynote “The Key Building Blocks in Surviving/Thriving in the Era of Exponential Technologies” presented by Al Eisaian, the CEO of IntelinAir. IntelinAir focuses on capturing actionable intelligence from aerial information. They combine drones, domain knowledge and sophisticated software to aid farmers’ decision making. While this service helps securing our food supply, Eisaian’s presentation gave us a lot of food for thought.

Eisaian started out with “If capital and organizational might are no longer driving the economy, what is?” Then he listed several important capabilities we can access today: Networks & Sensors, Infinite Computing, Artificial Intelligence and Robotics. He implied that these four areas are the foundation for his latest company, IntelinAir. And what’s his secret sauce for prosperity in general? Eisaian credits the “5 C Framework” for his continued success.

  • CARING: Find out what’s needed and why your solution for solving a specific challenge should exist and will be successful.
  • COMMITMENT: Make sure you and your team have a burning passion to bring this solution to market.
  • COMPETENCE: If you are not a domain expert, study this field and accumulate sufficient knowledge to really understand it.
  • CREATIVITY: Think out of the box, evaluate / mature your solutions by solving actual problems.
  • COMMUNITY: Review your solution within your close knit circle, check if your friends see its value, incorporate their ideas.
  • These 5Cs look promising and sound fairly easy to follow.

What else does Eisaian think is needed for success? Why doesn’t every company succeed with the basic “5 Cs”? Eisaian recommends to create an environment that really fosters innovation, such as:

  • Allocate time and resources for blue sky analysis and out of the box thinking, even allow for playfulness.
  • Inject reminders, focus the ongoing efforts, create visual aids, teach/explain/justify and critique the solution(s).
  • Create an innovation-friendly culture at your company and encourage risk; e.g. there are no failures, just lessons.
  • Infect the team with your passion; do not just rely on left-brain analytics, also utilize right-brain intuition and artistry.
  • Be unstoppable, become unreasonable when needed.

Last, but not least, Eisaian recommended several books and websites for the road to success:

After this big-picture view at innovation, let’s get to the topic that’s driving a paradigm shift in our industry.

Since the beginning of the year, interposer-based (2.5D), 3D-ICs and advanced wafer-level packaging (WLP) have received a lot more attention from the Trade Press than last year. Also, at this year’s DesignCon I noticed and heard from other attendees that a significant number of presenters talked about the value of interposers and advanced packaging to meet the increasing market needs for much higher Performance per Watt.

Important news closely related to these topics:

Tuesday morning I started with a tutorial about materials characteristics and modeling of their behavior up to 50GHz.

Yuriy Shlepnev, president and founder of Simberian, gave an in-depth presentation about theoretical principles of material characteristics and how to accurately model dielectrics and conductors to develop cost-effective and reliable ICs, packages and boards. Chudy Nwachukwu, applications engineer at the Isola-Group talked about these materials from a more manufacturing-centric perspective, and Scott McMorrow, from the Teraspeed Consulting Group, shared his vast experience in high-speed system design with the audience. Many of their statements confirmed that system scaling into smaller PCBs and fewer (multi-die) ICs will make it easier to meet customers’ demand for more performance per Watt.

In the afternoon John E. Bowers from UC Santa Barbara presented a broad range of photonics capabilities and photonics benefits for information transmission over thousands of miles, for data centers and “down” to the benefits within ICs.

Bowers talked about germanium being the most common substrate for photonics and showed how to merge photonics and CMOS on interposers, and at the die-level. He mentioned that IC packages introduce not only technical challenges for optical transmission of signals, but also significant additional unit cost. UC Santa Barbara has a lot of experience with Photonics ICs (PICs) and works closely with major semiconductor- and materials companies (Intel, HP, Infinera, Corning,..) as well as other universities (e.g.: SUNY) on increasing the photonics value proposition.

On Thursday afternoon I was able to attend a very informative EDA presentation from Mentor Graphics’ John Park.

Single design tool that aggregates, manages, and optimizes cross-domain systems. (Courtesy of Mentor Graphics)

He outlined Mentor’s approach to the increasing demand for an IC-Package-Board Co-Design flow. Park talked about the traditional approach – designing IC, package and board in isolation, then spending a lot of time and effort to make them work together, in spite of different design tools, conflicting naming conventions, diverging key objectives and of course separated development groups. Today most customers demand a less time-consuming, lower risk and more cost effective EDA solution. Mentor developed Xpedition® Package Integrator (XPI), a user-friendly, high productivity IC-package-board design flow. XPI enables these development groups to exchange data, optimize pin assignments, component placements and other parameters across all three domains and not only reduce the number of iterations, but also cut development time and unit cost.

You are welcomed to download – at no charge – the 324-page Multi-die IC Design Guide I compiled in 4Q2015, with great support from 25 companies, representing many parts of the 3D IC EcoSystem.

Like in previous years, I prepared this Design Guide to complement the Design Tutorial I moderated at last December’s 3D ASIP Conference, and distributed it to more than 100 companies in December. In the meantime I received lots of feedback and questions, therefore I updated my portions of the Design Guide and posted the updated edition (2016.1) on my website at www.eda2asic.com .

Also, considering the rapid progress of advanced packaging technologies in 2015 and the, most likely, accelerated pace they’ll experience in 2016, I have started already to request inputs for the 2016.6 edition, to be distributed at the Design Automation Conference in June and at Semicon West in July 2016.

Input deadline for the 2016.6 edition is Tuesday, April 19, 2016. Please contact me at Herb@eda2asic.com or 408 981 5831, if you want your services, tools, materials or equipment capabilities in support of design and/or manufacturing of interposer-based ICs (2.5D), vertically-stacked dies (3D-ICs), wafer- or panel processed multi-die ICs included in the 2016.6 edition.

2016 will bring a lot of changes to Semiconductors and supporting industries. Let’s prepare for them! ~ Herb