2015 Retrospective and Outlook for 2016: 3D NAND Flash One-upmanship

2015 Retrospective and Outlook for 2016: 3D NAND Flash One-upmanship

“On average since 1885, the yearly height record has gone up by 10 feet (3 meters) each time. Since the 1960s the pace has picked up to 16 feet.” This is not 3D NAND Flash but skyscraper heights in a recent article in The Economist (the power of visual data presentation!).

Similarly, 3D NAND height, as in the number of device layers, has become a metric for one-upmanship between the Flash manufacturers. August’s Flash Memory Summit was carefully preceded by declarations of 48-layer tall 3D NAND technologies from Samsung, Toshiba, and SanDisk while SK-Hynix revealed their plans to “prepare for its first production volumes” of a 36-layer chip in the third quarter of 2015 and “complete the design of a 48-layer triple-layer cell (TLC) in 2015”.

Despite all these announcements, Samsung remained the only 3D NAND manufacturer in 2015 to have real products with their 950 Pro SSD incorporating their 32-layer chip.

The NAND Flash market and analyst communities clearly need a single number to act as a proxy for manufacturing health, strength, and roadmap length and it’s interesting to see how quickly the 3D number of layers has taken over from 2D smallest half pitch (20nm, 15nm 1Xnm, 1Ynm, 1Znm, 10nm-class and so on).

Nevertheless, it was nice to see how Micron/Intel came up with their version of 3D NAND that deviates from the others in two main aspects, namely, floating gates used for charge storage instead of charge trap silicon nitride; and active circuitry underneath the 3D cell columns.

Before I launch into my predictions for 2016 and look back to see how accurate I was for 2015, let me spend a wee bit of time on this novel and intriguing floating gate approach.

Figure 1 - The Micron/Intel vertical channel Floating Gate 3-D NAND structure.

Figure 1 – The Micron/Intel vertical channel floating gate 3-D NAND structure.

Figure 1 shows my version of Micron/Intel’s structure as derived from their International Electronic Devices Meeting  (IEDM) presentation in December 2015.

An excellent analysis has already been done by Chipworks where details of materials, process flow and chip size are given.

From the data given in their paper, I work out a physical cell size per layer of between 30,000 nm2 and 36,000 nm2 which is about the same as Samsung’s V-NAND number. 

Notice the fundamental structure is similar to others in that a vertical cylindrical annulus of polysilicon is used as the channel. However, the use of a floating gate instead of charge trap silicon nitride is a nifty bit of engineering (used for its “proven reliability” according to the authors).

Figure 2 – A close-up of the Micron/Intel vertical channel Floating Gate 3-D NAND structure with the Inter-Poly Dielectric (IPD) synthetically pared back to reveal the Floating Gate.

Figure 2 – A close-up of the Micron/Intel vertical channel Floating Gate 3-D NAND structure with the Inter-Poly Dielectric (IPD) synthetically pared back to reveal the Floating Gate.

To make the encapsulated floating gate noticeable, check out figure 2 where I synthetically pared back the IPD.

For the really curious, I ferreted out one of the relevant patent applications showing how the floating gate is localized to each layer.

Since the channel body is not metallically connected, erasing takes place in a similar manner to the Toshiba/SanDisk 3-D NAND architecture using a so-called gate-induced leakage current at a channel junction.

Questions arise about how easily such an approach would work as more layers are stacked and whether Micron/Intel can capitalize on their “proven reliability” but, for now, it remains an attractive engineering feat.

Well, that was 2015 in a large nutshell. How accurate were my predictions from last January?

Here are the results: Samsung will come out with a close-to-50-tall structure (they announced a 48-layer); Intel’s foaming will lead to the almost inevitable SSD appearance of their chip (haven’t seen it yet); Micron will dip more than a toe into the water by giving more technical details of their structure (including the so-called “revolutionarily” different ones from Samsung’s approach but the same thing as Intel’s) (they presented their floating gate approach at the IEDM as described above); Toshiba/SanDisk will push 2D further by shaving off more nanometers to get to “sub-15nm” but still be reticent on their 3D approach (haven’t seen sub-15nm yet but they announced their 48-layer).

So about 50% right. Not bad at all! Let’s see if I can do better this year.

For 2016, I predict (and I need a better score than above): Samsung will appear with an SSD with their 48-layer chip and will “announce” a greater-than-60-layer chip; Micron/Intel will release an SSD with their 32-layer floating gate chip; Micron/Intel will give more technology/design details of their floating gate chip (that’s “in the bag” since they have an upcoming ISSCC presentation in February on a 768Gbit 3 bits/cell chip); some sub-15nm 2D NAND technology will be presented (also “in the bag” since Samsung of all people is presenting a 14nm 128Gbit chip at the same conference but I’ll only take the points if another company follows suit); Toshiba/SanDisk will announce SSD’s with their 48-layer chip but details will be kept close to their chests; alternative 3D NAND technologies will continue to be published indicating the limits of the present vertical channel approaches.

And again like last year, perhaps, just perhaps, another approach may break through that reaches lower cost that others cannot reach.

Let’s compare notes in a year’s time. ~ AJW