The IEEE International Electronic Devices Meeting (IEDM) been one of my favorite conferences for many years. Early in my career, I worked with Roger Haken at Texas Instruments on some of the work he published on materials for trench DRAM. Later on, the papers presented at IEDM helped me help predict the future of semiconductor manufacturing, and create my forecasts on CVD and etch for the industry.

The crowd lines up to check in at IEDM 2019 registration

IEDM 2019 showed that the conference continues to stay true to its roots, with papers spanning all semiconductor technology, and authors presenting research on what I would call near-term technology that is either in mainstream production or will be emerging in the next year or two. However, there are also papers on future technology such as Quantum compute chips, Ferroelectrics for DRAM technology, and gate-all-around (GAA) technology for next-generation logic devices. From a microelectronics perspective, it’s a bit like Alice’s Restaurant, you can pretty much get any microelectronics topic that you want. The blog will give a quick summary of the sessions I was able to attend during the week.

Next-generation Logic

As Moore’s Law has slowed, there have been some changes in the papers presented at the conference. In the early ’80s and into the ’90s memory was the technology driver and memory technology papers took the spotlight. In the late 90’s and 2000, the conference moved into the era of what I called “The Transistor Wars, where the logic or next-generation SRAM transistors were in the limelight. These sessions were typically entertaining as you had a head-to-head comparison of the transistor and device technology that would be released in the coming year. This year there was only one such paper by TSMC on their 5nm process. While it was nice to see the emerging technology paper, it was a bit anticlimactic as very little data was presented. This is unusual for an IEDM paper, as the committees typically require a great deal of rigor for papers to be accepted.

3D Logic

There is a great deal of activity on how to continue increasing transistor density.  I once called this “Moore’s Law in the Third Dimension”.  The logic manufacturers are taking cues from 3D NAND and starting to stack transistors or look at how to reduce the transistor footprint.  GAA or Nanosheets looks to be the natural transistor evolution from finFET technology. Multiple papers demonstrating GAA were presented.  Variations on the GAA technology included vertical GAA.  IMEC presented a potential future transistor concept called Forksheet, which builds the N and P transistor back-to-back with a dielectric post or wall in-between. The technology is targeted for 2nm and has the potential to reduce the transistor footprint.

Monolithic Semiconductors

With advances in process technology, monolithic logic transistors are becoming closer to reality. Several of the papers CEA-Leti presented discussed depositing materials such as amorphous silicon, or a metal oxide, and then manufacturing a transistor. Perrine Batude, of CEA-Leti, presented during a tutorial on monolithic semiconductors and was also a co-author on several papers that demonstrated a wafer bonding technique where the next level channel is bonded to the previous transistor. Then the next transistor is manufactured on top. Batude believes that the toolbox for monolithic devices is ready and they will begin to emerge in the manufacturing fabs fairly soon.  One of the advantages of monolithic technology is that you can place a higher mobility material on top of the base transistor, as was demonstrated by Intel using MOCVD GaN on top of a silicon PMOS using a layer transfer technique. Monolithic technology will create some interesting semiconductor opportunities in the not-too-distant future. First in the sensor area according to Batude, and then possibly in other microelectronic areas. Figure 1 demonstrates some of the possibilities for 3D sequential integration.

Figure 1. Special focus on 3D sequential integration. (Source: CEA-Leti)

Heterogeneous Compute by Packaging

The chiplet revolution is moving forward rapidly.  Herb Reiter will have more detailed comments in his blog. However, by using packaging techniques, multiple semiconductor technologies can be placed in the same package. This is enabling designers to move the memory closer to the logic processor to help reduce latency in the system which is critical for emerging AI and neuromorphic applications.

Memory is Back

While Memory never left, the pendulum at IEDM has swung back towards memory. Onboard memory technologies are becoming more critical for heterogeneous compute applications and were a major focus at the IEDM. STT-MRAM appears to be emerging in commercial devices, and resistive memories continue to be discussed in many applications especially neural networks. Limiting data movement is one key to lowering energy consumption and improving latency in neural network systems. At the Applied Materials evening presentation, it was pointed out that by 2025 10-15% of the global electric supply could be used by AI learning. That’s a lot of solar panels.  Developing memories and systems that can help reduce energy consumption will be important to sustainability.

IMEC LETI Next-generation Computing

Emmanuel Sabonnadiere, CEO of Leti. and Luc Van den hove, President of IMEC, kick off the first joint IMEC-Leti workshop at IEDM 2019.

IMEC and CEA-Leti joined forces to kick off the week at IEDM with a focus on next-generation computing. This was the first joint presentation at IEDM, as in the past they have had separate events. The keynote presentation by Subshi Mitra works to address the need for better silicon and systems for heterogenous computing to address the challenges facing the industry. Figure 2 proposes multiple onboard memory strategies combined with advanced 2D materials such as carbon nanotubes. Mitra’s group at Stanford and Skywater foundry have successfully built a ReRAM device using carbon nanotubes. The keynote helped to set the theme for the week at IEDM, as the electronics industry currently has a strong focus on heterogeneous computing.

N3XT Computation immersed in memory. (Source IMEC-Leti workshop 2019 IEDM)

IMEC and Leti researchers then discussed some key areas of research. Alexandre Valentian explained how moving memory closer to the edge helps to reduce power consumption. This can be achieved by stacking and connecting both horizontally and vertical memory to bring critical memory closer to the compute to help reduce power consumption and latency.

Figure 3: Distributed memory-centric edge AI computing architecture. (Source IMEC-Leti) workshop 2019 IEDM

Diederik Verkest discussed how using analog compute in memory accelerators for machine learning can improve both speed and power (Figure 4). The work at IMEC has demonstrated a record efficiency 2700TOP/s/W, which is significantly lower power and higher speed than the current chip solutions available on the market. With the concerns over the power needed for ML, it will be interesting to see how quickly this research gets picked up by IMEC’s partners.

Figure 4: Source IMEC-Leti Workshop 2019 IEDM.

Next-generation computing cannot be mentioned without discussing quantum computing. However, while Google, IBM, and Intel are making multiple claims about quantum computing the technology still has a long way to go as the hardware is still in its infancy. Being able to make qubits in silicon could help to proliferate quantum computing.

Figure 5: Where does quantum computing stand? (Source: CEA Leti)

The importance of independent semiconductor research and development is critical to the success of the electronics industry.  The IMEC-Leti partnership joins two of the leading independent research and development organizations. I look forward to the partnership producing many creative solutions to help propel the semiconductor industry into the future. ~ D. Freeman

Dean Freeman

Dean W. Freeman, Chief Analyst at FTMA, has over 36 years of semiconductor manufacturing and…

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