Almost 500 years ago Walter Raleigh was born in England, rose rapidly in the favor of Queen Elizabeth I and was knighted in 1585. In 1587 he initiated the founding of Raleigh. Last week he welcomed – appropriately dressed – about one thousand semiconductor experts to the 50th International Symposium on Microelectronics at the Raleigh, NC, Convention Center (Figure 1). If you look closer at thi... »
When planning the 24th EDPS, the organizing committee, chaired by Shishpal Rawat, former Intel executive, took a number of bold steps EDPS was traditionally held in the spring. We moved EDPS to the fall because that’s a time when more new IC projects are being planned. After many years of holding it in Monterey, we moved EDPS to Milpitas to make it more easily accessible for Silicon Valley folks... »
Last week, September 13 to be exact, TSMC held its Open Innovation Forum (OIP 2017) Symposium at the Santa Clara Convention Center. Before getting into product and market details, allow me to share some of my general impression of this, as usual, very well-organized event. After several decades of experience with alliance management and ecosystem building, I see TSMC as the master of these discipl... »
California’s Wine Country attracts visitors from all over the world. They can enjoy the scenic countryside, historic places, golf courses, tennis courts, gambling and of course great wine and excellent food. How well can a highly technical conference compete with all these “distractions”? Please read about the sessions I attended and judge for yourself! The Inaugural Conference and Exhibitio... »
I am convinced that increasing device complexity, higher quality requirements (e.g. automotive and medical), as well as the need for faster production ramp-ups, will force our industry to pay even more attention to design-in quality, expand self-test, even add redundancy to control logic and interconnects. In addition, wafer-probe and final test need to be expanded. Therefore, attending the Test V... »
San Francisco’s Moscone Center (above), the traditional home of SEMICON West trade shows, is undergoing major reconstruction work. Looking at this picture of the South Hall you may ask yourself: “Can anybody organize a large trade show here and make it a big success?” My answer is: “YES, the SEMI team can! They did exactly this in July for SEMICON West 2017!” With some very creative spac... »
The 54th Design Automation Conference (DAC 54) at the Austin Convention Center was very different, compared to the last several years’ events. Walking the exhibition floor, listening to keynotes, SKY talks and CEO interviews I got the following key impressions: While still representing a big part of the audience, the grey-haired men (like myself) were less dominant this year. Many younger people... »
At the end of April, I attended the Internet of Things (IoT) Developers Conference at the Santa Clara Convention Center. Because our semiconductor industry is expecting that IoT applications will significantly contribute to revenue growth, I wanted to get the latest about: If, how, when, why and for which applications IoT designs will be introduced and ramped into high-volume production. General i... »
The keynotes outlined in Part 1 of IMAPS DPC 2017 Covers Range of High-tech Topics, including EDA were obviously very important, but a relatively small part of the entire conference. After the two keynotes on Tuesday morning, I listened to YOLE’s presentation, delivered by Santosh Kumar, and learned that the three big memory vendors (Samsung, Micron, and Hynix) jointly hold over 200 TSV patents ... »
The WeKoPa Resort near Phoenix was the venue for the latest IC packaging focused conference, IMAPS DPC 2017, which took place in early March. The exhibition floor and all the sessions I joined were well attended and covered a broad range of topics, including design tools and methodology demonstrations from both Cadence and Mentor Graphics (as of Friday, 3/31, officially re-branded “Mentor, a Sie... »
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