The semiconductor industry’s ability to coax more and more performance out of a chip has produced the most significant innovations of our modern era. We are starting to test the limits of how much we can squeeze onto a tiny piece of silicon, according to Sanjay Bali, vice president of marketing and strategy at Synopsys.
For decades, Moore’s law correctly predicted that companies could pack exponentially more computing power onto a single chip. However, that growth is slowing, precisely at a time when the market demands more sophisticated features from chip-powered technologies small and large, including everything from smartphones and sensors to intelligent cars and cloud servers.
In a recent discussion with Sanjay, guest blogger, Bob Smith, of SEMI’s ESD Alliance, examines exciting new trends in the chip industry and strategies to help innovative companies meet the evolving needs of an increasingly data-powered world.
Smith: How concerned should we be that Moore’s law has essentially “slowed down?” And how does the slowdown impact design and development for various industries, including advanced applications such as AI and high-performance computing (HPC)?
Bali: First of all, we should keep a healthy perspective on what’s happening. We’ve got a long way to go until we reach Moore’s law’s absolute limit in geometric scaling. As an example, new transistor architectures such as gate-all-around are continuing to advance scaling.
The scale complexity delivered by Moore’s law is still a very important component of innovation, but there are other forces at play–the diminishing power and performance returns and the increasing cost of new technology nodes. This runs counter to the market demands for innovative new products that must provide higher performance with lower power requirements.
We are seeing a significant change across many applications, including HPC, AR/VR, automotive, and mobile. There is a growing demand for Smart Everything that encompasses a fusion of big data, massive compute, and machine learning. Compounding the scale complexity of Moore’s law is now the systemic complexity required by new products to fuel the demand for Smart Everything. We call this the SysMoore era–the merging of Moore’s law scale complexity with systemic complexity–and it requires new innovations from silicon-to-system to unlock the vast potential in front of us.
Smith: Tell us more about how SysMoore is fueling new innovations.
Bali: The SysMoore era is giving impetus to rethink chip design to address emerging technology and economic challenges.
AI and domain-specific architectures are some of the recent innovations advancing chip development and helping accelerate the realization of optimal designs. Among the most important innovations that characterize the SysMoore era is multi-die 3D integration in advanced packaging. Multi-die systems of small dies or chiplets, often on different process nodes, integrated into a single package are proving to be a worthy option to meet aggressive power, performance, and area (PPA) targets.
The compact footprint of multi-die systems is valuable for mobile devices and the internet of things (IoT), where area is at a premium. At the same time, multi-chip integration provides added functionality and performance for technologies that require lots of computing power, such as data centers, cloud computing, and AI. We are witnessing a definite trend towards using multi-die 3D design technologies to address the pressing demands of system designs that must deliver high performance with low power in very small form factors.
Smith: How is multi-die or 3D IC transforming how chips are designed and produced?
Bali: We’re seeing a significant transformation from system-on-chip (SoC) to system-of-chips designs, catalyzed by the evolution of multi-die design. This introduces new challenges and complexities related to the integration of multiple dies or chiplets in 3D stacks, impacting the entire design and development process. These include increased functionality and packaging density, higher interconnect bandwidth and lower latency, reduced system power, heterogeneous integration for optimality, modularity (e.g., bespoke silicon and application-specific semiconductor solutions), and overall lower system cost.
To enable the design of multi-die systems, we need to look beyond piecemeal innovation to a holistic solution. This includes streamlining the design process with a more productive and efficient multi-dimensional design platform, encompassing planning, exploration, creation and integration, system implementation, test, analysis, and signoff.
We are observing that many multi-die designs are intended for systems with high requirements for safety, security, and resilience. A holistic, unified development approach provides an opportunity to further transform design and manufacturing by incorporating silicon lifecycle management to address the health of silicon, packages, and systems throughout their lifecycle with observation and monitoring.
Smith: What else must the industry do to navigate the SysMoore era successfully?
Bali: The limits of Moore’s law affect everybody, which means companies can’t simply operate in their own bubble. To speed the adoption of multi-die system technologies, the industry must work together to develop new standards for architectural and design methodologies that adequately meet the challenges posed by SysMoore. It truly takes a village, and to that effect, we’ll see growing partnerships across the entire chip ecosystem that will supercharge the design-to-manufacturing process.
Smith: What will a leading-edge chip look like in 5 years? What innovations will be needed to reach the next stage?
Bali: We expect chips to reach the trillion-transistor threshold within the next five years. Multi-die systems will continue to grow to meet the scaling demands of applications and will be denser and more complex. They will require highly modular design techniques with greater use of chiplets and improved architecture and partitioning. The use of AI and big data analytics to explore and manage volumes of data will be essential for meeting time-to-market goals. Design-technology co-optimization (DTCO) will evolve into system-technology co-optimization (STCO). The demands for safety and security will continue to grow, and these must be built into the design from the beginning. One thing that won’t change is PPA requirements driven by the end application will dominate the design process.
Overall, to advance chip design innovation, the industry needs to move even further to a system-level mindset. It’s not just about the silicon design: foundry recipes, advanced integration packaging, interconnect protocols, and methodologies for new challenges such as power distribution, thermal management, and mechanical stability, must be dealt with collaboratively. This expanded mindset, together with a rich industry ecosystem and tightly integrated toolsets, will enable efficient building of cost-effective trillion-scale products that are correct by construction and capable of meeting the needs of tomorrow’s applications.
About Sanjay Bali
Sanjay serves as Vice President for Marketing and Strategy for the EDA Group at Synopsys. In this role, he leads the business units’ overall strategy and manages all aspects of the product roadmap, go-to-market strategy, business development, ecosystem partnership, and custodianship of financial KPIs. Prior to joining Synopsys in 2008 as Director of Marketing for Physical Verification and Design for Manufacturing, Sanjay held engineering and product marketing positions at Intel, Actel Corporation (Microsemi, now Microchip), Mentor Graphics, and Magma Design Automation. He graduated from the National Defense Academy India, with a bachelor’s degree in science and served as a Lieutenant in the Indian Armed Forces (Navy) before entering the world of high technology. He holds master’s degrees in Computer Science and Business Administration from Santa Clara University, Calif.