3D In Context

About Herb Reiter

After more than 20 years in technical and business roles at semiconductor and EDA companies, Herb Reiter founded eda2asic Consulting, Inc. in 2002 to focus on increasing the cooperation between EDA suppliers and ASIC vendors. In this role Herb introduced innovative IC design tools to the major semiconductor vendors worldwide. In 2008 he expanded his scope into Multi-die ICs. As chair of the GSA’s 3D-IC Working Group (2008-2011) and as SEMATECH business development consultant (2012 + ‘13), he broadened his horizon to include interposers and 3D-ICs technology, semiconductor materials as well as manufacturing, metrology and test equipment. In 2014 + '15 Herb consulted with Si2, to encourage development and standardization of data exchange formats for Interposer and 3D-IC design flows. Since early 2016 he is consulting with the newly formed Electronic System Design Alliance (formerly EDAC), to accelerate market acceptance of Multi-die ICs, the essential building blocks for the emerging System Scaling methodology.
Herb attended 40+ Continuing Education courses at Stanford University, earned an MBA at San Jose State University and Master Degrees in Business and Electrical Engineering at the University and the Technical College in Linz/Austria, respectively. He can be reached at herb@eda2asic.com

Here are my most recent posts

U2U 2019 Conference Dives into 2.5/3D IC Design

U2U 2019 Conference Dives into 2.5/3D IC Design

Key advanced packaging technology influencers came out in force to discuss the status of  EDA tools for 2.5D/3D IC package design at the recent User to User (U2U 2019) Conference, organized by Mentor, A Siemens’ Business and hosted at the Santa Clara Marriott. Presenters from Wave Computing, ARM, Amkor, TechSearch International Inc., and Qualcomm lent their voices to the cause. Technology T... »

TSMC’s 2019 Technology Symposium highlights 25 Years of Innovation

TSMC’s 2019 Technology Symposium highlights 25 Years of Innovation

In 1994 TSMC, a small wafer foundry from Taiwan held its first Technology Symposium. Since 1999 I have had the privilege to work with TSMC and closely follow their success in building a powerful and cost-effective ecosystem for the fabless IC vendors and foundry business model. To measure their success in hard numbers, please check IC Insights’ 2018 revenue estimates here and see that TSMC has a... »

Update on  3D X-ray and DBI Technology for Advanced and 3D Packaging

Update on 3D X-ray and DBI Technology for Advanced and 3D Packaging

The Microelectronics Packaging & Test Engineering Council (MEPTEC) held its monthly meeting at SEMI in Milpitas on April 10.  Two speakers outlined their companies’ capabilities and demonstrated their own expertise in solving specific industry challenges. Tom Gregorich presented why and how Zeiss supports IC package inspection with 3D X-ray machines, then Sitaram Arkalgud conveyed the benef... »

FLEX/MSTC Keynotes Confirm: Our Customers Need System-level Solutions

FLEX/MSTC Keynotes Confirm: Our Customers Need System-level Solutions

From February 18 to 21, 2019, Monterey, CA, was again the venue for SEMI’s Flexible Hybrid Electronics (FLEX) and MEMS & Sensors Technical Congress (MSTC), conference. As in previous years, the joint keynotes, 2-track technical sessions, and more than 50 exhibitors demonstrated the synergies between these two industry segments and their fast pace of innovation. The entire conference focused ... »

DesignCon 2019 Shows Board and System Designers the Benefits of Advanced IC Packaging

DesignCon 2019 Shows Board and System Designers the Benefits of Advanced IC Packaging

Santa Clara’s Convention Center was home to DesignCon 2019 from January 29-31, 2019. This conference is well known for showing printed circuit board (PCB) and system designers the latest technology advances, enabling higher performance and lower power and lower cost solutions. Bootcamps, tutorials, keynotes, and many in-depth technical sessions offered engineers up-to-date information to make th... »

ISS 2019 Continued: Facing New Challenges and Opportunities

ISS 2019 Continued: Facing New Challenges and Opportunities

Just in case you didn’t have a chance yet to read part 1 of the ISS 2019 blog, covering day 1, it’s posted here. Technology and Manufacturing Trends Day 2 started with a keynote about the magic nanodevices can create, delivered byJo de Boeck, imec’s EVP and chief strategy officer. He emphasized that we need to find smarter ways to compute, store data and connect building blocks. De Boeck ... »

ISS 2019: Semiconductor Industry Faces New Challenges and Opportunities

ISS 2019: Semiconductor Industry Faces New Challenges and Opportunities

SEMI held its annual Industry Strategy Symposium (ISS 2019) at the Ritz Carlton in Halfmoon Bay, CA January 6-9, 2019. Many high-level executives represented key areas of the electronic products supply chain. Former government officials emphasized that our country’s leaders recognize the strategic importance of semiconductors. The theme of ISS 2019 was: “The Golden Age of Semiconductors: Enabl... »

Highlights From MEPTEC’s 2018 Heterogeneous Integration Symposium

Highlights From MEPTEC’s 2018 Heterogeneous Integration Symposium

The Microelectronics Packaging and Test Engineering Council (MEPTEC) held its annual heterogeneous integration symposium at SEMI’s headquarters in Milpitas, CA on December 5, 2018. Many manufacturing and test, as well as electronic design automation (EDA) and IC design experts, got together to present and discuss how to integrate heterogeneous functions in advanced IC packages to better meet cus... »

EDA Design Tools/Flows Targeting WLP Featured at IWLPC 2018

EDA Design Tools/Flows Targeting WLP Featured at IWLPC 2018

Wafer and panel-level packaging (WLP/PLP) offers technical and business advantages, compared to traditional IC packages. These cost-effective packaging solutions attracted more than 800 industry experts to the International Wafer Level Packaging Conference (IWLPC 2018) in San Jose’s DoubleTree Hotel at the end of October. In case you were wondering, a multi-die WLP design, created with the tools... »

Wally Rhines Discusses the Importance of EDA and Design at IWLPC 2018

Wally Rhines Discusses the Importance of EDA and Design at IWLPC 2018

At this year’s International Wafer-level Packaging Conference, almost 1000 semiconductor experts from all parts of the supply chain gathered at the DoubleTree Hotel in San Jose from October 23 to 25. Among them were also several electronic design automation (EDA) experts who discussed how to streamline die-package-board co-design. They explained how EDA tools enable higher performance per Watt a... »

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