Advanced SiPs Help More than Moore Reach Maturity

Advanced SiPs Help More than Moore Reach Maturity

Earlier this summer, 175 system-in-package (SiP) experts from all over the world met at the Marriott Hotel in Monterey’s Old Town at the IMAPS Advanced SiPs Conference. This conference focused exclusively on innovative SiP technology developments and trends, demonstrating that a significant part of the value creation is moving from the silicon to the package.

Nozad Karim, VP: SiP/System Integration and Electrical Engineering, at Amkor, offered a business perspective, using Amkor’s orders as an example: Communication applications represent 44% of Amkor’s business, while automotive and industrial represent 26%, computing 18%, and consumer 12%. He explained in great depth why and where it makes sense in these segments to utilize SiPs, to combine the needed functions in an advanced package.*

Challenges for Advanced SiPs

We learned that embedding 5G antennas in or on the package is a new challenge. They require conformal (= entire) or compartmental (= partial) coating of molded packages – to shield sensitive circuitry from electromagnetic interference (EMI) and to minimize signal radiation.

Embedded passives are in high demand. Amkor’s equipment is capable of processing components down to 008004. In mm, that’s a 0.25 mm long and 0.125 mm wide component.

Karim reminded IC and system designers to consider loss characteristics of interposer and substrate materials, surface roughness and other high-frequency effects to avoid signal loss, wasted power, and heat. Automotive cameras and lidar need a package with a window to function. He suggests closer and up-front cooperation between designers and packaging experts.

SiP Trends in Automotive

Romain Fraux, CEO of System Plus Consulting, focused on SiP trends in automotive. Most of the teardowns he showed are currently assembled on small PCBs. They could benefit from the smaller form-factor, lower power, and higher performance of advanced SiPs and modules.

Intel’s Hamid Azimi, VP Technology Group and Director, Substrate Packaging Development, presented Intel’s EMIB and Foveros capabilities and confirmed that customers are asking for larger and larger interposers, with more I/Os, tighter pitches and higher bandwidth, especially for computing and networking designs. (Figure 1).

Figure 1: Intel’s view of Advanced Packaging requirements. (Courtesy Hamid Azimi, Intel VP)

Rao Tummala, Director Emeritus of Georgia Tech’s (GT) 3D Systems Packaging Research Center (PRC), shared his vision for close cooperation between universities and industry, to accelerate development and deployment (D&D) of new technologies. He emphasized that today’s systems need more than Moore’s Law can offer and outlined his strategy for Georgia Tech’s Package Research Center – see Figure 2. On this slide please notice point 3.: Educate new INTER-disciplinary individual engineers!

In addition to the keynotes above, many excellent speakers from almost 40 companies, Universities and R&D organizations showed their progress in support of advanced packaging in electronic design automation (EDA) tools, materials, manufacturing equipment and process flows.

About one dozen exhibitor showed their capabilities on tabletops in the foyer, including Cadence as well as Mentor, a Siemens business.

The program also included a very constructive panel discussion on advanced SiPs, managed by Jan Vardaman and Urmi Ray, a start-up competition and last, but certainly not least, a “Sip at SiP” event – an exclusive wine and dine experience.

Where to Learn more about Advanced SiPs

Very focused conferences are excellent opportunities to get industry updates, network with experts in the specific field and avoid getting behind. Please consider the opportunities below:

  • For SiP technology updates join the 52nd IMAPS Conference in Boston, MA, from September 30 to October 3.
  • To use AI / ML for more efficient design and manufacturing of SoCs and SiPs, join EDPS 2019 in Milpitas October 3 and 4.
  • For MEMS and Sensors updates, join MSEC 2019 in San Diego from Oct 22 to 24.
  • For the latest about wafer/panel-level packaging, join IWLPC in San Jose, from Oct 22 to 24.
  • For reliability topics join the 16th International Conference on Reliability and Stress-related Phenomena in Nano and Microelectronics (IRSP) at San Jose State University from November 4 to 6.

Thanks for reading…Herb