Because memory represents typically about half the silicon content of a system, and multi-die packages typically combine many memory devices with one or more logic dice, I made it a point to attend both Yole Développement’s Executive Memory Breakfast and The Flash Summit on August 6th. I, along with about 100 other industry executives, had to get up very early to make the 7 am breakfast meeting and finish before the Flash Summit started. Our conclusion was: It was clearly worth it.
DRAM
Walt Coon, Yole, recapped several decades of tough times for the DRAM business, as many competitors in the U.S., then Japan, Europe, Korea and then Taiwan were fighting for market share of these memory devices. Coon also showed that after a significant supplier consolidation (see Figure 1, orange line), the margins improved, up to the 40s, in this capital-intensive industry.
NAND Flash Memory
Yole’s Mike Howard outlined the last two decades of developments in the NAND market, including the rapidly increasing CapEx per bit and negative operating margins. Figure 2 shows NAND Q2 market shares and operating margins for the main players.
All these vendors are now losing money. This fact encouraged Howard to speculate how these suppliers may consolidate further. He projected that a combination of Intel’s memory business with Micron may make sense; or Micron & Western Digital, or SK Hynix & Toshiba memory, or Western Digital & Toshiba or even an SK Hynix & Intel AND Micron & Toshiba & WD team to be formed to compete with Samsung’s memory business and the emerging Chinese memory giant, YMTC. He also pointed out that solid-state-disks (SSDs) consume about 50% of today’s Flash production. In addition, modules combining DRAM and Flash are getting more popular, as our current component-focused semiconductor business moves towards (sub)system solutions.
3D NAND Memory
After all these high-level business discussions, Belinda Dube, from System Plus Consulting, part of the Yole Développement family of companies, took the stage and dove deep into technology topics, especially around 3D NAND. In addition to memory technology details, Dube showed a comparison between Samsung’s generation-4 and generation-5 V-NAND (Figure 3). While the cost per wafer is likely to increase by 30%, the smaller generation-5 dice will enable 20% lower cost per bit.
Simone Bertolazzi’s presentation focused on emerging non-volatile memory technologies that are either in development or available today. He stated that today’s finFET-based SRAM technology cannot be scaled further and will, most likely, be replaced by STT-MRAMs. He clearly categorized Intel’s 3D X-point as phase-change memory (PCM) technology. Bertolazzi said ST Microelectronics is in the process of qualifying their PCM technology for high-temperature automotive applications. He also confirmed that STT-MRAM can operate at higher temperatures than DRAMs, which is an important criteria for stacking logic and memory in a multi-die package. In addition to the memory technologies overview table (Figure 4) Bertolazzi outlined a pricing and density comparison of these technologies (Figure 5).
After the expert presentations and Q&A with them, we got the opportunity to network with the many experienced people in the audience. Another very valuable way to spend an early morning. Thanks for reading…Herb
