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MEMS Packaging Market is Growing Faster Than The MEMS Devices Market

MEMS Packaging Market is Growing Faster Than The MEMS Devices Market

According to Yole Développement (Yole), the MEMS packaging market will grow from US$2.56 billion in 2016 to US$6.46 billion in 2022, showing a 16.7% CAGR[1] over this period. The MEMS packaging market’s value is growing faster than the MEMS device market’s value: respectively, a 16.7% CAGR for packaging versus 14.1% for devices, during the period 2016 – 2022. Under this dynamic context,... »

The FAST route to the Top of the TSV Mountain

The FAST route to the Top of the TSV Mountain

. While on a recent visit to UnitySC in Grenoble, France, I spent some time visiting with a semiconductor process equipment company that shares the same cleanroom space: KOBUS. Named for a genus of the African antelope for its elegance and speed, the company has developed a unique approach to deposition for through silicon via (TSV) metallization processes (barrier, seed and fill) combining the pe... »

Cast your votes for the 2016 3D InCites Awards

Cast your votes for the 2016 3D InCites Awards

This year’s awards will be decided entirely by your industry peers through this online voting process. The nominees are listed below by category. You must be registered and logged in to vote. Please vote for one per category. You may vote one time in a 24 hour period. Standings will be displayed until July 5, but to keep it interesting, we will hide the standings for the last three days of votin... »

Path Finding and 3DPF

Path Finding and 3DPF

In the past year, I have written short pieces explaining how Path Finding methodology can proactively help identify viable solutions or reactively identify solutions if something changes during manufacturing. The next few blogs will look at specific examples using a PF tool to help separate the ‘wheat from the chaff’. Signal Assignments When I was designing ASICs/SOCs at VLSI Technology, we no... »

Why is it Taking so Long to Ramp Interposer and 3D IC Designs?

Why is it Taking so Long to Ramp Interposer and 3D IC Designs?

And what are we going to do about it in 2015…? A moment ago I finished reading my predictions for 2014. I wrote them on January 11, 2014, almost exactly one year ago. After convincing myself that I was roughly on target, I am going to stick my neck out again, and, hopefully, give you some food for thought. I hope you can agree with me that my previous predictions, emphasizing good prospects for... »

Popping the Cork on 3D IC at IEEE 3DIC 2014

Popping the Cork on 3D IC at IEEE 3DIC 2014

The IEEE International Conference on 3D System Integration (3DIC) was held in Kinsale, Cork, Ireland in December, 2014. The three day conference covered all 3D IC topics, including 3D process technology, materials, equipment, circuits technology, design methodology, thermal effects and applications. The 2014 conference was very successful with a great atmosphere with vigorous discussion and lots o... »

SEMICON West 2014: Supplier Updates for 2.5D and 3D Processes

SEMICON West 2014: Supplier Updates for 2.5D and 3D Processes

SEMICON West 2014 brought its usual flurry of supplier announcements on new equipment and process improvements; but there weren’t as many focused on 3D technologies as there have been in past years. This is likely due to the fact that some players are holding off until 3D hits it big and they get some return on their investment. But for the true die-hards, they’re not letting a little thing li... »

KLA Tencor: CV310i Wafer Edge Inspection and Metrology Module

KLA Tencor: CV310i Wafer Edge Inspection and Metrology Module

CIRCL CV310i module is an advanced Wafer Edge inspection, metrology and profiling system tailored for Advanced Wafer Level Packaging. Simultaneous wafer edge inspection and metrology enables comprehensive data collection from all zones comprising the wafer’s edge: top and bottom near-edge; top and bottom bevel; and apex. Testimonial Some of the critical process steps in the 3D integration proces... »

SSEC: Wet Etch Process for TSV Reveal

SSEC: Wet Etch Process for TSV Reveal

SSEC’s wet TSV reveal process achieves -/+ 0.7% Si thickness uniformity under the appropriate post grinding conditions with fast throughput. The two-step process starts with a spin etch for a smooth, fast etch at 10µm/min. The etch is stopped 2µm above the TSVs and then finishes with a selective etch process (Si:SiO2 >2,500) to endpoint on the TSV based on Si thickness measurements done on ... »

Akrion Systems: Vacuum Prime and Dry

Akrion Systems: Vacuum Prime and Dry

Akrion Systems’ vacuum prime and drying technology enables the use of a wet immersion method to introduce liquid chemicals or rinse water throughout the entire HAR feature prior to the oxide etching step.  Pulling a vacuum below the saturated vapor pressure of water, draws liquid into the entire feature, enabling a uniform oxide etch. Testimonial Surface preparation is important for 3D IC, part... »

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