Increasing the Conductive Density of Power Packaging
Mar 03, 2021 · By Shaun Bowers · 3D In-Depth, Materials, Processes and Technology
Design View all
EDPS 2020: An Inside Look at the Manufacturing-centric Presentations
Like many other industry conferences, the Electronic Design Process Symposium (EDPS 2020) had to go virtual. Not only did it keep our audience safe but allowed us to attract almost 200 registrants worldwide. Thanks to sponsorships from – ANSYS, Cadence, CEDA, Intel, Mentor – A Siemens Business, and Synopsys –...
DAC 2020 Addresses Chiplet Design and Integration
In the early days of ASIC technology, only logic library elements and basic I/Os with up to 10s of transistors were available for customizing gate arrays and/or logic functions in standard cell chips. And then, “megacells” (a.k.a. Functional Blocks, Semiconductor IP Blocks), comprised of 100s, even 1000s, and more transistors...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
System-on-Chip Disintegration is Underway
We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...
Latest Posts - Page 24
Suppliers offer solutions to TSV formation challenges
As part of the 3D tracks at both this year’s International Wafer Level Packaging Conference, held October 27-30 in...
Discussion Summary: Overcoming weaknesses in dry processes for TSV metallization
This week’s online forum with Alchimer’s executive team, Steve Lerner, CEO; Kathy Cook, Director of Business...Terepac begins pilot production of printed silicon ICs
Terepac Corporation has begun shipping samples of its ultrathin, flexible, silicon-based products to selected customers from its plant in Waterloo,...Taking the “pick” out of pick-and-place
Up until now, although it was possible to manufacture miniscule (e.g. 175µm square) RFID and wireless sensor chips using advanced...Alchimer Introduces AquiVia Deposition Process
Alchimer S.A. announced that its AquiVia deposition process is ready for implementation. AquiVia process can reportedly reduce overall cost...
Bringing Transparency to 3D Integrated Structures – Olympus Confocal IR Microscopy
Metrology is consistently one of the more challenging areas in the semiconductor field. Whether it’s the monitoring of ultra-small...
Inside CEA-Leti’s 3D Toolbox
Grenoble-based research institute CEA-Leti’s progress is fueled by a single mission: create innovation and transfer it to industry. The goal...SUSS MicroTec workshop zeroes in on wafer thinning and handling issues
Last year, it was all about through silicon vias (TSVs), this year, it’s all about everything else needed to...
IMEC and SUSS MicroTec to collaborate on wafer bonding for 3D integration
SUSS MicroTec and IMEC have entered a joint development program to develop permanent bonding, temporary bonding...Trends and challenges for thin wafer processing
Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are...3d is hot at SEMICON West
Given the building momentum around 3D integration schemes and the attention it's getting as the semiconductor bright spot, it's...
At IMAPS 2009, IBM Bradley McCredie gets real about scaling
It looks like it’s time to throw in the towel on scaling. According to Bradley McCredie, Ph.D., IBM fellow and...IWLPC 2009 speakers put 3D up front
Sure, 3D integration and packaging isn’t the only game in the semiconductor industry town, but even at events like last...Alchimer introduces seedless wet deposition; eliminates entire step from TSV stacking
Alchimer S.A.,provider of technology for the deposition of nanometric films used in both semiconductor interconnects and 3D through-silicon vias (TSV),...Jisso International Council 2009: Defining 3D
The Jisso International Council (JIC) successfully completed its 10th annual meeting at the facilities of Minatec in Grenoble, France,...