Process Control and Inspection for High-Value Advanced Packages: It’s Complicated
Oct 15, 2020 · By Francoise von Trapp · Test and Inspection
Design View all
DAC 2020 Addresses Chiplet Design and Integration
In the early days of ASIC technology, only logic library elements and basic I/Os with up to 10s of transistors were available for customizing gate arrays and/or logic functions in standard cell chips. And then, “megacells” (a.k.a. Functional Blocks, Semiconductor IP Blocks), comprised of 100s, even 1000s, and more transistors...
An EDA Perspective on Today’s Advanced Packaging
In my alliance management roles at electronic design automation (EDA) companies, I arranged many presentations to convey the benefits of EDA tools to IDMs, fabless IC vendors, and wafer foundries. Some of our EDA marketing people passionately presented their products’ strengths and demonstrated in-depth EDA knowledge. However, speaking fast, with...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
The Future of Non-volatile Memory
Part 4 of the series, The Triumph of Quantum Mechanics at the Heart of Solid-State Data Storage, continues with the future of non-volatile memory. The figure above is a concept for 3D stacking of Flash devices. A thin-film field effect transistor with a silicon nitride as charge reservoir and a tunnel oxide....
Latest Posts - Page 24
SUSS MicroTec workshop zeroes in on wafer thinning and handling issues
Last year, it was all about through silicon vias (TSVs), this year, it’s all about everything else needed to...
IMEC and SUSS MicroTec to collaborate on wafer bonding for 3D integration
SUSS MicroTec and IMEC have entered a joint development program to develop permanent bonding, temporary bonding...Trends and challenges for thin wafer processing
Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are...3d is hot at SEMICON West
Given the building momentum around 3D integration schemes and the attention it's getting as the semiconductor bright spot, it's...
At IMAPS 2009, IBM Bradley McCredie gets real about scaling
It looks like it’s time to throw in the towel on scaling. According to Bradley McCredie, Ph.D., IBM fellow and...IWLPC 2009 speakers put 3D up front
Sure, 3D integration and packaging isn’t the only game in the semiconductor industry town, but even at events like last...Alchimer introduces seedless wet deposition; eliminates entire step from TSV stacking
Alchimer S.A.,provider of technology for the deposition of nanometric films used in both semiconductor interconnects and 3D through-silicon vias (TSV),...Jisso International Council 2009: Defining 3D
The Jisso International Council (JIC) successfully completed its 10th annual meeting at the facilities of Minatec in Grenoble, France,...
