Maskless Lithography Addresses Shift Toward Heterogeneous Integration and 3D Packaging
Jul 12, 2022 · By Thomas Uhrmann · 3D In-Depth, Processes and Technology
Design View all
Considerations in Power Amplifier Package Design
Understanding the role of compromises and trade-offs in the design process Electronic packages serve many purposes including protecting, connecting, and cooling a device. If any of these are done improperly, the chip is rendered inefficient at best or useless altogether. For that reason, the design, construction, properties, and capabilities of...
Design-for-test for 3D IC Designs Comes of Age
In the era of more-than-Moore, 3D IC is the new scaling approach adopted by the marketplace. Progress has been made throughout the semiconductor ecosystem in bringing 3D ICs designs to the mainstream, including design-for-test (DFT). First came 2.5D Design-for-test The industry got some practice for the challenges of 3D IC...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
System-on-Chip Disintegration is Underway
We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...
Latest Posts - Page 26
At IMAPS 2009, IBM Bradley McCredie gets real about scaling
It looks like it’s time to throw in the towel on scaling. According to Bradley McCredie, Ph.D., IBM fellow and...IWLPC 2009 speakers put 3D up front
Sure, 3D integration and packaging isn’t the only game in the semiconductor industry town, but even at events like last...Alchimer introduces seedless wet deposition; eliminates entire step from TSV stacking
Alchimer S.A.,provider of technology for the deposition of nanometric films used in both semiconductor interconnects and 3D through-silicon vias (TSV),...Jisso International Council 2009: Defining 3D
The Jisso International Council (JIC) successfully completed its 10th annual meeting at the facilities of Minatec in Grenoble, France,...