3D Integration Research, SEMATECH Style

SEMATECH’s story is one that is truly built upon the essence of collaboration.  SEMATECH is not a traditional research center.  Rather, it is a technology research consortium that exists to serve the best interests of its worldwide members and partners. Originally established in Austin, TX as an experiment in combining government and industry to further the development of semiconductor technologies, academia was added to the mix when the College of Nanoscale Science and Engineering (CNSE), in Albany, NY, joined the consortium. One thing is certain, the membership list is pretty impressive, including powerhouse companies such as Intel, Global Foundries, IBM, Hewlett Packard, UMC, Samsung, TSMC, and Qualcomm.

According to Sitaram Arkalgud, director of interconnect at SEMATECH, the consortium has become more flexible as it has evolved, particularly within the 3D integration program. While the member IDMs participate in everything SEMATECH does, there are members that only belong to the 3D group, or associate members who are members of only one aspect of the 3D group, such as that pertaining to equipment processes or material. Member companies have access to equipment and structural module builds, and share research data.

Setting up Shop
In the past two years, SEMATECH has gone through infrastructure changes that are proving mutually beneficial to everyone involved.  In Austin, SEMATECH owned its own facility. In Albany, it is an anchor partner at CNSE’s $6.5B Albany NanoTech Complex, one of more than 250 international semiconductor companies that collaborate on campus (Not to mention the Giants football team).  According to Richard Brilla, VP of strategy, alliances and consortia at CNSE, one of the key programs for the transition of SEMATECH from Austin to Albany was the 3D integration program. First of all, there was “a significant investment by New York state” to support the SEMATECH program at CNSE, along with growing investments by IBM that include the development of a computer chip packaging center. Rather than duplicate efforts, it made sense to work together and leverage 3D integration work to both programs. SEMATECH has access to CNSE’s 300mm CMOS tool set, research and data, and likewise, CNSE has access to tools, research and data belonging to SEMATECH.  For example, CNSE has developed a 65nm test vehicle which the team uses to test 3D –processes in collaboration, such as looking at the effects of TSV on CMOS.  Indeed, CNSE assignees make up half the SEMATECH research team. The partners share 80,000 sq. ft. of Class 1 cleanroom space.

When it comes to 3D integration, a partnership with SEMATECH is extremely advantageous, because as Michael Liehr, associate VP of business, alliances, and consortia at CNSE puts it, “3D is supported by the small and medium size equipment suppliers.”  Arkalgud concurs, noting that having a tool at SEMATECH is a good position for a company to be in, because of shared risk and cost, and access to research data. It also allows for exposure to the major players.  For example, notes Liehr, one goal could be to develop tools to support the requirements and expectations of a partner company, such as Intel, because Intel sends in assignees to review the tools they care about. CNSE provides a facility to bring tools here and do unit process evaluation, which is attractive for companies who can’t afford the infrastructure to do it on their own,  noted Arkalgud.  Additionally, SEMATECH has all the analytical support in areas where they lack expertise or funding to provide independently, thus providing a basis for shared research.

New York State investment to date of $800M provides support for infrastructure and facilities at CNSE, explained Brilla, and attracts other companies to get involved, since the investment funds CNSE’s unparalleled technological infrastructure rather than specific companies. Another $6B has been leveraged so far in private funds in what represents a significant return on investment.

Getting Down to Business
Technical feasibility isn’t enough to satisfy the members of SEMATECH.  For them, the goal is high volume manufacturing (HVM).  So when the research consortium established its 3D interconnect program, the first thing they did was to identify the challenges preventing HVM, and set out to focus efforts there.  According to Klaus Hummler, there was a weak spot in materials and the tool infrastructure, as well as gaps in the supply chain. To accelerate progress in the development of cost-effective and manufacturable 3D TSV solutions, SEMATECH focuses on unit process integration development.  “Our goal is to integrate unit processes and tools in a process flow that makes sense for products,” explained Larry Smith.  Specifically, the program focuses on materials, equipment, and unit process development; integration of the three; reliability; and ecosystem development.

According to Hummler, SEMATECH is targeting  via-middle processes, or TSVs formed after front-end of line (FEOL) and before back-end-of-line (BEOL) before 3D stacking; wafer thinning before 3D stacking; back to face bonding; die-to-wafer (D2W) bonding (also collective hybrid bonding). Additionally, TSVs measure 5µm in diameter with a 10-50µm pitch and 20-50µm depth.

Smith explained that part of the unit process development is evaluating manufacturing readiness.  Once the tool is installed, it’s put through tool hardening to prove it can handle 3D wafers in HVM environment.  SEMATECH now boasts the 1st consortia-owned 300mm TSV tool line, comprising both EV Group’s manual wafer align bond tool (EVG 540) and its next-generation Gemini platform; an automated SET FC300 die bonderscanning acoustic microscope from Sonoscan; thickness monitor from MTII; and IR microscope from Olympus; TSV depth and profiler from Lasertec (TSV300IR);  Rudolph’s AXi935 all surface inspection tool; access to AFM, SEM, TEM, and HRP via ISMI and CSNE;  a Telius SP UD from Tokyo Electron, for TSV reactive ion etch; a Stratus plating tool from NEXX Systems;  wafer backgrind/edge trim tool from Okamoto; a Brewer Cee Module for spin/bake materials characterization; in addition to access to state-of-the-art FEOL and BEOL tooling for standard CMOS processes.

Andy Rudack, who heads up the metrology development, explained that for the first year of the program, the big push was getting the tools in place. Based on wafer starts and specification for subsequent 3D research, the tools were added as needed. For example, the unique Lasertec tool that has the TAMAR sensor installed for TSV depth measurement with unlimited aspect ratio didn’t need to be re-engineered to meet SEMATECH’s needs.  Rudack says they’re just “shaking out the bugs” and getting information on the tool and technique, which will be shared at SPIE this year.  Then there’s the IR microscope from Olympus that started as a regular visible microscope platform and was converted to a first-of-its-kind IR/Overlay metrology tool. Rudack says that with it, you can see through silicon, making it useful for defect work.

Building Consensus
At SEMICON Taiwan, Nokia put the stake in the ground, saying they will target a wide I/O single package 4 DRAM stack, combining the best of both worlds, wide I/O for performance, and TSVs for form factor (thin, multi-die stack).  Hummler says this is a perfect vehicle for Nokia to implement without over extending itself, because it doesn’t require all the elements to be completely ready (e.g., true 3D co-design tools). Wide I/O DRAM on logic presents the lowest risk opportunity.  Nokia plans to go to HVM by 2013.

For two years, the 3D team has built the program to represent processes, working towards industry consensus and converging process and equipment solutions with interest in getting out of the lab into HVM.   However, they recognize the gaps in the ecosystem in the EDA and test areas. As such, Smith and Rudack have been charged with addressing those gaps.  SEMATECH was very active in 2010 holding workshops, forums and surveys to understand where everyone is.  Workshops have focused on stress management and metrology, and they are engaging with SEMI to accelerate the development of new standards.

Overall, the 3D research team is very optimistic and excited about HVM for 3D TSVS becoming a reality before too much longer.   And when SEMATECH’s members are behind it, you can pretty much count on it happening.