Keith Cooper, Technology and Development, SET North America reports from 2010 IMAPS International , where he attended the 3D Panel, “Roadmap, Technical and Business Progress of 3D Integration and Packaging”.

At the recent IMAPS Annual Meeting in Raleigh, NC, a panel of 3D experts addressed a series of questions moderated by Prof. James Lu of RPI.   While individual opinions on the panel varied on minor issues, the group spoke largely with one voice. Panelists included industry experts including Dr. Urmi Ray of Qualcomm, Dr. Phil Garrou of Microelectronics Consultants of North Carolina, Dr. Klaus Hummler of Sematech, Dr. Dorota Temple of RTI, Dr. Nicolas Sillon of LETI, and Rozalia Beica of Applied Materials’ Semitool division.

Q: Is TSV ready?  What is the timeline for adoption?  Which of the key markets will be first adopters?

Panelists: Qualcomm is on an aggressive timeline for implementation of 3D with TSV’s, with commercial engagement foreseen in 2012.  Nokia is likewise pursuing 3D heavily and is pointing toward product introduction in 2013.  Xilinx recently announced the use of TSV’s for their FPGA devices.  CMOS image sensors have already used vertical integration but are not truly a 3D IC scheme. Flash memory will not be an early adopter of 3D integration due to historic price pressures, but DRAM on logic is a strong candidate to do so.  TSV fabrication processes are already established in 15 fabs worldwide, but manufacturing readiness needs work. 3D packaging, on the other hand, is up and running (e.g memory stacking with multi-level wire bonding).

Q: Do we really need logic-on-logic?  What about thermal management?

Panelists: Re-partitioning of microprocessor nodes (into strata to reduce interconnect length) may be key to reducing risk for some logic designs.  The heat problem may not be as bad as once suspected, and progress on thermal management is good.

Q. Do we agree on the evolution from C2C to C2W to W2W? Is W2W best for memory?

Panelists: All 3 methods (of stacking) have their advantages and their proper place.  For true heterogeneous 3D integration, W2W will not be practical due to different wafer suppliers (fabs), diameters, CTE mismatch between materials, and the KGD issue (C2C and C2W bond only known good die, while W2W bonds entire wafers). DRAM stacking is a likely candidate to converge upon W2W stacking due to price pressure and similar die sizes, but this method does not support the present practice of binning memory by performance and selling the best-performing die at significant premium.

Q: What are areas of recent technical progress?  What are barriers to adoption?  Are any qualified 300mm fab lines available for TSV production today?

Panelists: There has been good progress across many fronts due to some high-quality engineering work, with specific milestones met in defining standards and Electronic Design Automation.TSV pilot production is available, but the community needs more work done in thinning and de-bonding of wafers, process integration and the availability of manufacturing-qualified equipment with appropriate cost-of-ownership. TSV development fabs are widespread, but the road from lab to fab must be paved before widespread adoption can take place. A killer application is needed to introduce TSV’s on a wide scale basis.

Q: What is 3D application space?  What are the roles played by the contributors? What are key business roadblocks to TSV implementation?

Panel: Collaboration is the key to progress; consortia and institutes are playing a key role by participating in such activities as driving standards which will enable widespread adoption. Fabless companies like Qualcomm can and have played a key role in defining roadmaps and driving solutions.  Wide bandwidth memory is a key application and driver for 3D technology, and consumer applications such as cellphone/PDA continue to play a major role.  3D technology will get a real boost when it is demonstrated with real ICs, not just test vehicles.

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