Silicon Photonics: the Next Killer App for 3D ICs? and more from the R&D Community

Silicon Photonics: the Next Killer App for 3D ICs? and more from the R&D Community

First it was going to be memory stacks, then it was Wide I/O DRAM on Memory, and now, as commercialization of 3D ICs gets pushed out further, will it be Silicon Photonics that drives 3D ICs to volume manufacturing? That was the opinion expressed by Michael Liehr, executive VP of Executive VP CNSE, during the SEMICON West 2013 R&D Panel – “A Conversation on the Future of Semiconductor Technology”, which I attended on July 10, 2013.

In addition to Lier, the panelists hailed from some of the world’s leading R&D Centers for micro- and nanoelectronics including Daniel Armbrust, President & CEO SEMATECH; Dr. Laurent Malier, CEO of CEA-Leti; and Luc Van den hove, President & CEO imec. SEMI Americas president, Karen Savala, presided over the discussion, posing prepared questions to the panelists covering all the current hot points including vertical transistors (FinFETs), 3D-IC, 450mm, and EUV. I tuned in mostly to what was being said about 3D ICs.

In addition to pointing to Si photonics as the next 3D killer app, Liehr said that 3D as a technology is slower than expected to take off for two reasons: one, its more expensive than traditional packaging solutions, and therefore we have to focus on getting the cost closer to traditional packaging solutions. (Personally, I disagree with this theory. We need to stop putting 3D ICs in the same category as traditional packaging solutions, as the performance benefits clearly outweigh traditional packaging. Rather, we should be focusing on looking at system level cost, as Ajit Minocha, of GlobalFoundries, suggested in his keynote speech, and where 3D ICs can be a cost enabler as an alternative to scaling.)

The second reason is due of the number of applications 3D is suited for, few could be considered “killer apps” – or an application that would drive millions of parts. “Until we find a technology that truly takes advantages of its capabilities, it won’t take off to the degree that we would like,” he said. That’s when he pointed to integrated photonics on an interposer, which he hopes will eventually lead to a quantum leap in performance.

Van den hove says its his (and imec’s) belief that 3D IC stacking is an important technology, and imec has merged its packaging and interconnect departments into one team because they want to work on the interface. “We’re bringing together the total ecosystem,” said Van den hove. “We have two worlds that have to meet: the foundry and packaging worlds.” He explained this is why imec has brought in fabless companies and EDA suppliers. Fabless companies have to start thinking about changing architectures to bring in 3D, he explained. As process flows converge, he says he believes this technology will be an essential platform for high performance systems, agreeing with Liehr about the significance of optical interconnects and silicon photonics.

Armbrust suggested that it’s the cost/performance ratio that is important. “At the right cost, are you getting the performance advantage?” He asked. “You need a high volume application to drive that.” He said that for the past two years, SEMATECH has focused on standards, and that the industry has really come together to establish an ecosystem, particularly in 2.5D. “We’ll get there.” He said. “As an industry, we’ve spread out our 3D efforts in many ways. If we were to do it over again, we’d focus in certain areas, with more thought into future collaborations.”

Malier interjected that Leti was the first to fully develop 3D ICs into manufacturing with CMOS image sensors (generally considered 2.5D, but with the introduction of backside illumination (BSI) image sensors by Sony in 2012, qualifies as a 3D IC product). He said the current core of research focuses on shrink and densities, reducing the “dead zone” and coming up with more economic and cost effective solutions, such as increasing aspect ratios.

Looking to the future overall, we can expect to see some changes to the research ecosystem, whether we’re talking about 3D ICs, 450, EUV or what have you. System companies need early pathfinding to anticipate how products will migrate. Combined efforts in modeling and simulation will be critical, as system company demand drives the profitability of the industry.

Armbrust noted that one challenge facing the supply chain is the affordability of the infrastructure. “We (SEMATECH) need to provide easy access capabilities that are shared, and adapt our programs in different areas,” he said.

Van den hove says he expects to see a foundry/fabless model that works together more intensely during the development phase. He called it “an integrated fabless model” based on a need for system architects that have an early awareness for what the technology revolution is going to be. This change was triggered by 3D integration technology. How it will influence system architecture is why fabless companies have started to join programs, he explained. Liehr concurred. “End users are more involved in discussions to learn how to integrate themselves,” he said.

According to Liehr, there is also an EU initiative that encourages R&D institutes to get involved and take advantage of each others strengths, so as to not duplicate efforts. That way the end-user doesn’t have to pay for something twice. As an example, Malier talked about how Leti won’t invest in 450mm, but will support the effort where they can, in metrology, for example. The are also not working on FinFets, but rather focusing on FD SOI to add value by bringing alternative choices to designers.

Armbrust probably summed it up best. “We are entering a period of extreme uncertainty that brings us back to our roots as a start-up community.” ~ F.v.T.