ASMC 2015: Has the Wonderment of Semiconductors Become a Presumption?

ASMC 2015: Has the Wonderment of Semiconductors Become a Presumption?

The 26th annual SEMI Advanced Semiconductor Manufacturing Conference was held in Saratoga Springs, NY, May 3-6, 2015.  ASMC 2015 drew a record number of attendees to the lovely old town of Saratoga (aka the Queen of Spas), a town which is conveniently situated just miles up the road from GLOBALFOUNDRIES Fab 8 in Malta, NY, and which is just a reasonable drive away from The College of Nanoscale Science and Engineering in Albany, GE Global Research in Niskayuna, NY, the IBM facilities in Fishkill and Yorktown Heights, NY, and the IBM plant in Burlington, VT.

Not to mention being hailing distance from several other distinguished colleges and universities in the area.

In other words, The region is pretty much a hotbed of semiconductor research, development, and manufacturing, if you hadn’t already thought of it that way.

The corridor running from Vermont, through various Mohawk and Hudson River towns, is a corridor that Tom Caulfield, senior vice president and general manager of Fab 8, GLOBALFOUNDRIES, and ASMC 2015 opening keynote speaker, refers to as “Tech Valley.”

ASMC 2015 Glass BowlIt’s a valley of opportunity, based on the value proposition that arises from being fully invested in semiconductor manufacturing, a value proposition being supported by any number of enthusiastic believers, local and distant, starting with the highest officials in New York State government, from their seats in Albany, all the way to financiers in Abu Dhabi, and the Advanced Technology Investment Company, which has backed so much of GLOBALFOUNDRIES’ progress to date.

But is semiconductor manufacturing in trouble?  Is the magic gone?

“Riding the Wave of Silicon Magic” was the theme at this year’s SEMI Industry Strategy Symposium in January; at ASMC 2015 it was “Semiconductor Manufacturing: Keeping the Silicon Magic Alive” that was the topic addressed by the discussion panelists (DARPA, GE Global Research, Lam, RIT, Semiconductor Advisors) and moderator (me) commenting on whether “technical showstoppers, lack of critical investments, and failure to nurture a curious, well-educated workforce might cause the semiconductor industry to falter.”

(Short answer: No.)

Consider this: in a recent piece from The New Yorker, Tad Friend, in a lengthy profile of Marc Andreessen, pre-eminent Silicon Valley / Sand Hill Road venture capitalist, managed to avoid entirely any mention of semiconductor manufacturing.

Chip fabrication is now so far up the food chain for Silicon Valley that the thinking goes something like this about how today’s present wonders (mobile phones, the Internet) manage to exist:  “’Uber is built on the efforts of thousands of people in the Valley,’ the investor Naval Ravikant said. ‘On the back of the iPhone and Android and G.P.S. and battery technology and online credit-card payments, all stacked on themselves.’”

Pardon me, Naval, pardon me, Silicon Valley, but, what about the silicon?

Robert Maire, Semiconductor Advisors, in his ASMC 2015 closing keynote, put it like this: “The wonderment of chips has become a presumption.”

A friend from the Bay Area writes “I worry that the general public thinks the US is doing well in technology because we have a bunch of 25-year-olds writing apps….”

Fortunately, we have more than just a bunch of 25-year-old app writers working in “high tech,” (high tech now seeming to be synonymous with the app economy, not the manufacturing economy – how did that come to happen?).

Beyond the app-writers, we also have a wealth of both experienced and recently-educated semiconductor manufacturing, development, and research engineers who have made, and are continuing to make, great things happen in the world of microelectronic device fabrication.

Annual reports about which are made at SEMI ASMC, capturing the geist of our current semiconductor zeit.

One report is this: on the 3D IC – TSV side, the technology has worked its way into general semiconductor fabrication process flows to the point that, while there was a dedicated session (Session 14) on 3D/TSV at ASMC 2015, there were a number of other 3D/TSV papers spread throughout the other AMC sessions.ASMC 2015 Glass Blocks

Papers like these: Methodology to Estimate TSV Film Thickness Using a Novel Inline “Adaptive Pattern Registration” Method (GLOBALFOUNDRIES, Rudolph); Plasma Dicing Trench Depth, Copper Step Height and Roughness Measurements with an Optical Profilometer (Infineon, Fries Research and Technology); and Post TSV Etch Cleaning Process Development using SAPS Megasonic Technology (ACM Research, Inc., SEMATECH).

In the dedicated 3D/TSV session the papers presented were: Deep Trench Capacitor in Three Dimensional Through Silicon Via Keepout Area for Electrostatic Discharge Protection (IBM Systems and Technology Group); Enhanced Etch Process for TSV and Deep Silicon Etch (Lam Research Corporation); Precision Wafer Bonding Process for Future Cost-Effective 3DICs (Nikon Corporation/Osaka University); and Yield enhancement and mitigating the Si-chipping and cracking in ultra-thin 20μm-thick 8 and 12 inch LSI wafers (Tohoku University).

The Lam paper was of particular note, as Lam seems to have solved the basic issue of balancing Bosch Process etch rates in deep silicon TSVs with the large “scallops” typically created when silicon etch rates are maximized; they have done so by instituting very fast gas switching between the deposition and etch portions of the Bosch Process cycle, and showed very convincing results in the talk.

Were there signs of heterogeneous integration in this semiconductor manufacturing conference?

Indeed there were.

ASMC 2015 Glass ArcsIn the Q&A session following his opening keynote, Tom Caulfield was asked about integrating III-V materials with silicon. His take is that people (people at GlOBALFOUNDRIES?) are actively looking at this, it’s not here yet, but that work in this area will not stop.

And there were these two papers as well, III-V heterointegration’s foot in the door: Backside and Edge Clean of III-V on Si Wafers for Contamination Free Manufacturing (Tokyo Electron Technology Center America, College of Nanoscale Science and Engineering); and 300mm Wafer Level Sulfur Monolayer Doping for III-V Materials (SEMATECH, SCREEN Semiconductor Solutions Co.).

Dr. Caulfield’s general message to ASMC 2015, a somewhat conservative message, was one about the need for the semiconductor industry to balance the will to consolidate with the will to collaborate (pace, Nietzsche).

That’s natural and reasonable, given the vast investments required now for new wafer fabs running advanced semiconductor manufacturing technologies ($12B+ for 10nm FinFET fabs on 300mm wafers).

But, big as those investments are and conservative as the money is, we as an industry continue to employ and nurture engineers who are not shy about continuing to push the envelope, engineers whose thinking goes like this: “If you don’t take any risk then you don’t know semiconductor manufacturing.”

From Pittsburgh, PA, thanks for reading.  ~PFW