R&D Round-up Part 2: CEA-Leti rolls out TSV and Non-TSV Demonstrators

Reporting progress for CEA-Léti was 3D program manager Mark Scannell, who notes an overall shift in what’s driving Léti’s 3D developments. In its early phase, he said, it was a “technology push.” In 2009, that moved to a mature phase driven by “an application pull”. As such, Léti has industrial partners coming to them looking for prototyping, and its goal is to accommodate the needs that exist right now, in addition to looking down the road. “As things develop, the roadmap seems to get clearer for us,” notes Scannell.

Léti’s 3D research involves mid and high density solutions for both TSV and non-TSV 3D integration. In the realm of high-density TSV work, Scannell says Léti has focused mostly on via-last, because “it gets to applications quicker because (via last) chips need minimum adaptation, whereas via middle requires intervention.” He explained. “However, we’re working on process blocks, so a lot of what we’re doing in via last is applicable to via middle.”

Léti has demonstrated a TSV integration process using a direct SiO2 bonding for both die to wafer (D2W) and wafer-to-wafer (W2W). Next on the agenda is to complete the integration process with Cu direct bonding because this will enable 400°C TSV last without changing the base wafer process; CMOS fab compatibility allows for back-end-of-line processes after stacking; the resulting process blocks are flat and easy to package; it enables one face-to-face connection; is compatible with D2W, W2W or multi-chip stacking; it’s scaleable, and doesn’t require thin substrate handling; and the process blocks are interchangeable with via-middle integration.

Recent achievements in the mid-density TSV category include a feasibility demonstration in which a 45nm technology was stacked on a 130nm silicon interposer. Driven by the needs of the CMOS image sensor market, this milestone is significant because of the convergence of technologies. Scannell explained that Leti is looking for ways to push legacy fabs further. “You can change the flavor of a product by putting a chip from a high-end fab on top (of an older technology), thereby minimizing the amount of manufacturing being done in the high-end fab when it’s not necessary.” He said.

Léti’s near term technical goal is to combine these demonstrated technologies for high-performance applications, partitioning for performance, cost, and manufacturing benefits. Scannell says to look for convergence of high density and mid density with silicon inteposer technology in 2011.

The driving force of the non-TSV work being done at Léti is similar to that of the active Si interposer. Customers who don’t have access to foundries, but get chips delivered off the shelf are looking for a way to stack those. SoLéti developed a low-density process called Via Belt technology, that uses NI micro-inserts and Ni pillars that can be put on an RDL wafer and have universal flip chip attached to it without any preparation. Scannell says this process has already been demonstrated to stack a CPU on memory for smart card applications. For high-density non-TSV solutions, Scannell talked about early stages of 3D monolithic integration that uses a thin film transfer, and is interesting for highly miniaturized CMOS image sensors.

Summing things up, Scannell says at Léti, progress is being made, and developments are ongoing. One thing is for sure, notes Scannell, “3D is a very interesting place to work.”

Part 1: 3D Progress at RTI International

Part 3 will report on MIT Lincoln Labs