At last month’s 3D Architectures for Semiconductor Integration and Packaging Conference, coordinated by RTI International, three government-funded research institutes – RTI, CEA-Leti, and MIT Lincoln Laboratories reported on the status of their progress in the 3D integration space. The diversity of approaches discussed underlined, once again, the complexity of this market and the myriad of opportunities it offers.
To stock what Dorota Temple, RTI Fellow, calls “RTI’s 3D-integration Technology Toolbox”, the institute has focused on different process and material approaches including through wafer vias, integrated passives, heterogeneous integration compound semiconductors, high-density vertical interconnects, fine-pitch metal-metal bonding, advanced flip chip, and silicon carrier technologies. The goal is to create “IC-foundry agnostic” 3D integration technologies; meaning those that are flexible and can be applied across the industry. She cited examples of RTI’s research in different areas of 3D integration landscape; specifically calling out 3D packaging, 3D silicon interposer technology, and 3D ICs.
In the 3D packaging realm, RTI has put efforts into optimizing Cu via fill approaches for through silicon vias (TSVs). One outcome of this work is what Temple called unfilled “barrel vias” suited to via last approaches and simpler for integration. Additionally, for filled vias, RTI is collaborating with Enthone and Entrepix on a process to remove Cu overburden using a 2 step CMP process. This work is expected to be presented at ECTC 2010.
According to Temple, key modules in 3D silicon interposer work at RTI involve large area multi-level metal structures, such as power/ground planes, interconnected by TSVs from the wafer backside. This research resulted in a VC funded spin-out called siXis Inc. The start-up has applied 3D silicon interposer architecture to embedded computing modules.
However, of all the projects being run at RTI, Temple says the work developing 3D IC process modules (wafer thinning, polymer bonding, die-level and cu-cu bonding) has been “the most challenging and the most rewarding.” In collaboration with DRS technologies, RTI has worked on 3D IC modules. She reports achieving test bars that Temple says will allow for the development of functional, high-performance IR imagers. This work, funded by DARPA, was largely in collaboration with DRS Technologies.
One last are of 3D work that falls outside the realm of 3D interconnect research, yet related to 3D systems integration is what Temple termed “3D enabled passives”. The concept is to replace 2D thin film passives with 3D inductors, transformers and capacitors. The advantage, Temple noted, is that a 3D integrated passive layer does not risk ICs to process yield, is not subject to known-good-die (KDG) issues, is not dependent on IC real estate, and is not subject to the thermal budget of IC die.
To enable prototypes of 3D microsystem solutions, Temple noted that RTI has recently expanded its lab space to include 5000 sq.ft. of class 100 clean room space. Additionally, it has acquired 200mm equipment to complement existing 150 and 200mm process capabilities. Ongoing collaborative efforts with government, commercial and academic organizations are expected to further RTI’s achievements in 3D integration.