Atrenta Inc., provider of Early Design Closure® solutions that improve design efficiency throughout the IC design flow, has signed a multi-year collaboration agreement with CEA-Leti.The joint development work defined in the collaboration agreement will take place at Atrenta’s R&D center in Grenoble.
“3D design and advanced power reduction represent two areas of significant interest for the microelectronics community that CEA-Leti serves,” said Dr. Ahmed Jerraya, head of design programs and research director at CEA-Leti. “We look forward to collaborating with Atrenta France SAS to advance the state of the art in these areas.”
The work defined by the collaboration agreement will focus on two primary development areas. First, techniques to analyze, predict and reduce the power consumption of advanced microelectronic devices at the early stages of design, including the architectural and register transfer language (RTL) levels. And second, the analysis and partitioning of 3D stacked die devices, also at the architectural and RTL levels. Stacked die devices are now being made possible in part by through silicon via (TSV) semiconductor process technology advances.
“Atrenta has a long history of collaborating with our customers in the Grenoble area,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “We look forward to working with those customers alongside the substantial technical resources of CEA-Leti. This organization provides an excellent environment for advanced research.”