Taking 3D Integration to the Next Level

Taking 3D Integration to the Next Level

There is no rest for the weary. Just because we can finally declare that 3D ICs are in production doesn’t mean we’re done working on it. To the contrary, efforts are ongoing at research institutes like imec in Belgium and Leti in France to take 3D integration to the next level.

Driven by what imec’s Luc van den hove called “the intuitive internet of things (I-IOT)” the heat is on to make 3D ICs more cost efficient so they can be implemented not only as memory in high-end data centers to support the increase in bandwidth the IoT is calling for, but also eventually into the wearable devices themselves to allow for computations to take place on the wearable devices themselves, while also helping to make them smaller and more invisible to the wearer.

As Eric Beyne, director of 3D integration at imec, explained to me, to communicate energy more efficiently between an IoT node and the external world, it’s better to do the processing within the node. “The more data you have to send out, the worse it gets,” he said. Active interposer technology that’s now in development both at imec and at Leti can help because first of all, it’s a testable device, (it’s difficult to test non-functional passive interposers). It also enables power regulation within the substrate, which is needed because in real-world IoT devices, communicating with sensors requires high voltage of current.

Beyne talked about a 15-year-old concept developed by the e-Cube European project that integrated technologies that generally don’t integrate well, such as integrated wireless technology, sensing, data processing, and energy harvesting, and using an interposer, built one system-in-package (SiP) to create a 3D integrated functional unit that was 14mm x 14mm. “The difference between now and then is that we now have TSVs to make it more efficient,” said Beyne.

Fabricating TSVS are the easy part, noted Beyne. Efforts in imec’s 3D program are focusing on areas like micro-bump joining technology and chip-packaging integration (CPI). There’s lots of ongoing work in micro-bump scaling down to 10µm, and 5µm.


Figure 1: options for 3D SOC mixed node stacking (image courtesy of imec)

Beyne also talked about work in 3D SoC mixed node integration, in both die-to-wafer and wafer-to-wafer configurations (Figure 1). Die-to-wafer offers more design freedom, but requires 5µm pitch µbumps when scaling to 5nm and below. He also discussed various options for wafer-to-wafer stacks. In one scenario, both wafers have FEOL and BEOL processing, and finished wafers are joined using Cu-Cu hybrid bonding for a high-density micro-bump connection. Processing afterwards is minimal, and works for via reveal and via last. Another scenario is when the top wafer has FEOL and some BEOL processing. High AR TSVs connect metal pads on the top and bottom wafers. Additional BEOL layers are added after wafer stacking for signal redistribution.

LetiDay at SEMICON West was all 3D all the time, with Going Vertical as its topic. I sat down with Leti CEO, Marie-Noelle Semeria, who explained three game-changing technologies that have happened at Leti this year: fully depleted silicon on insulator (SOI), Silicon Impulse, and CoolCube.

According to Semeria, FD-SOI will be a new standard for Internet of Things (IoT). “This is a key turning point for an institute like Leti,” she said. At SEMICON West, Leti announced that GlobalFoundries will support FD-SOI in manufacturing.

The second game changer is Si Impulse, a design center for the EDA ecosystem, to give it access to emerging technologies including non-volatile memory, embedded memory, and photonics. Si Impulse provides an EDA environment with open access to multi-project wafers.

The third, and in my opinion the most significant game changer is CoolCube, the monolithic 3D IC approach that uses a low-temperature process to stack transistor layers. Semaria describes CoolCube as a low-cost scaling alternative, as it provides the next generation node performance using current nodes, thereby avoiding the development cost of the next generation. Details on CoolCube’s technology are available in this Knowledge Portal Post.

According to Semaria, a CoolCube test vehicle is available and they are able to demonstrate that all the building blocks are there, and partners are evaluating the technology’s benefits. The goal is to introduce CoolCube into the semiconductor flow. Leti is working with Applied Materials, Qualcomm, ST Microelectronics, and IBM, and is in discussions with foundries. The intention is to demonstrate it next year. “Coolcube is a disruptive technology. It can enable local scaling or generic
heterogenous systems integration,” she said. For example, NEMS on CMOS integration can be achieved, thanks to Coolcube. More than 20 companies have indicated interested in discussing the capabilities of the technologies.

Another program Leti hosts is IRT Nanoelec, an R&D consortium that is supported by the French government and is yet another way to interact with Leti and its ecosystem partners. Severine Cheramy, Leti’s 3D IC lab manager, explained that Nanoelec’s open program puts together a full supply chain to complete this work. “We work in cooperation with the design team to make sure the technology makes sense from the design perspective and vice versa,” she said. The team includes a designer, CAD tool, technologist, and equipment partner.

Figure 2: IRT Nanoelec's 3D NoC demonstrator.

Figure 2: IRT Nanoelec’s 3D NoC demonstrator.

Just prior to SEMICON West, IRT Nanoelec announced it had realized an innovative 3D chip, called “3DNoC” to demonstrate the use of 3D stacking technology in scalable, complex digital systems-on-chip (SoCs.) Cheramy showed me the 3DNoC (literally – check out Figure 2), which comprises two identical logic die stacked on top of each other using TSV and Cu pillars as interconnect. The die are stacked on an off the shelf ball-grid array (BGA) package. Cheramy explained the significance of this work as demonstrating that two IP design blocks can be aligned and stacked together. While this demonstrator addresses baseband processing, Charamy notes that the methodology ad design bricks are transferable to other applications. The technical details of this work are explained fully here.

In this case the objective was to show that for digital processing applications, you can stack two die together to get to the performance of the next node. As previously mentioned, CoolCube has a similar objective at the transistor level to achieve “true 3D IC.”

Charamy cited other areas of focus for the 3D IC program at Leti that are in various stages of development, such as Cu-Cu direct bonding for logic blocks and logic gates at finer pitch than Cu pillar. She reports achievement of 6 layers of metal stacked on six layers of metal in the back-end-of-line (BEOL). Another fine-pitch enabling technology for high density TSVs in the works is MOCVD for filling high aspect ratio TSVs. At the proof-of-concept stage is IntAct, a chiplet on active interposer demonstrator.

Like Eric Beyne, Charamy pointed out that there is a lot more to 3D integration than TSVs. She encourages any company who has something to contribute that would add value to the Nanoelec program, to consider joining the program. ~ F.v.T.