Beyond Transport Modes: Balancing Cost and Speed in Semiconductor Logistics
Dec 29, 2025 · By Robin Knopf · Blogs, From Different Dimensions
Latest Posts - Page 15
3D ICs Eliminate the Memory Wall
The adoption of 3D ICs allowed the elimination of the “Memory Wall” using a new memory architecture and through silicon...
Probe Test for 3D Integration: A Thousand Mile Journey
When we look back at the last 10 years, it’s really been a series of baby steps to move the...
3D Powered: From Image Sensors to Artificial Intelligence
Paul Werbaneth, Nor-Cal Products The widespread deployment of 3D stacked CMOS Image Sensors (CIS) in consumer electronics, namely smartphones, by...
3D InCites Turns 10: A Brief Analysis of the 3D Journey
Yann Guillou, Applied Materials I cannot believe 3D InCites is already turning 10! As wise people say, time flies! Taking...
Perspectives on the Cost of Fan-out Wafer Level Packaging vs. Flip Chip Packaging
Recently, I read a paper published in the 2017 IMAPS Device Packaging Conference proceedings, titled “Cost Comparison of Fan-out Wafer Level...
Advanced Packaging Trends – Part II: Solving Lithography Challenges
Part 1 of this advanced packaging (AP) article series focused on solving photoresist (PR) strip and under bump metallization (UBM)...
Advanced Packaging Trends, Part I: Solving PR Strip and UBM/RDL Challenges
Over the years, the semiconductor industry has relentlessly focused on shrinking gate dimensions to drive performance. This focus has now...
European 3D Summit 2018: Fraunhofer Tour and Presentations
This year’s European 3D Summit in Dresden, which highlighted “Heterogeneous Integration Driving 3D”, was led off by presentations and a...
Can We Thank Aristotle for Heterogeneous Integration?
A couple of years ago we may not have predicted that in 2018 there would be a growing demand for...
Breakthroughs in 3D Chip Technology Lead to Cooling With Microfluidics and 3D Printing
2017 saw a clear breakthrough for 3D chip technology in commercial products. Before then, the industry had looked rather...
2018 Industry Outlook: It’s Time to Get Serious about 5G
While the entire semiconductor industry is buzzing about explosive and sustained growth well into the 2020s driven by smart everything...
A Material Solution for the Growing 3D Imaging Market
With emerging markets developing for augmented reality (AR), virtual reality (VR), facial-recognition security systems, advanced human/machine interfaces and other 3D...
2018 Outlook for Advanced Packaging Materials
Advanced packaging is moving mainstream as manufacturers continue to seek ways to improve device performance beyond traditional scaling. The semiconductor...
A Tribute to Gilles Poupon, CEA-Leti’s Advanced Packaging Pope
Sitting in the bus on the way back from Grenoble to Airport Lyon, I am reflecting the last two days...
MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained
Multichip module (MCM), system-in-package (SiP), system-on-chip (SoC), and heterogeneous integration are all important semiconductor packaging technologies. They deserve to have, at...
Warpage Issues in Fan-Out Wafer Level Packaging
As you all know, warpage is a critical issue for fan-out wafer/panel level packaging. Many people like to talk about it,...Advanced Packaging Adds Value and Reduces Cost for Future Semiconductor Products
Yole Développement (Yole) confirms the consolidation of the advanced packaging industry, that is showing a steady growth in revenue of...
Are Glass Substrates the Next Option for Fan-out Packaging?
As you all may know, in most fan-out wafer level packages (FOWLP) such as embedded wafer level ball grid array...
The Advancement of Device Packaging – A Resume on IMAPS DPC 2017
As part of the organizing committee, we believe this year’s IMAPS Device Packaging Conference really fulfilled what the announcement promised...
