Jan Vardaman, Author at 3D InCites

3D ICs Eliminate the Memory Wall

3D ICs Eliminate the Memory Wall

The adoption of 3D ICs allowed the elimination of the “Memory Wall” using a new memory architecture and through silicon via (TSV) technology. While individual ICs became faster with each process node, the communication between the chips was constrained by limited pin counts, power hungry I/Os, and PCB-space limitations. Assembly of multiple dies into one package enables extremely wide busses b... »

Realistic Expectations for 3D IC Products in 2015

Realistic Expectations for 3D IC Products in 2015

In an era where people expect instant everything, the development of the market for 3D ICs with TSVs has not met many expectations. But for those who really understand how long it takes to bring a new technology to maturity, it should be no surprise. It has taken memory companies more than 10 years of development to bring out commercial 3D IC products with TSVs. Other than die stacking for image s... »

3D IC Notes from SEMICON Taiwan 2014

3D IC Notes from SEMICON Taiwan 2014

I attended the 3D IC Technology Forum at SEMICON Taiwan 2014, where many of the discussions focused on the latest memory announcements in 3D ICs from Micron, SK Hynix, Samsung, and Tezzaron. While the world still waits for the introduction of a Wide I/O mobile DRAM and logic part, memory is clearly moving into production. The focus of Taiwanese OSATs in the 2.5D space, such as SPIL and ASE, is to ... »

The Small Scale Systems Integration and Packaging (S³IP) Center

3D ICs for High Performance Systems

A recent IEEC and IEEE CPMT workshop held on October 16, 2013 at Binghamton University in New York examined the status of 2.5D and 3D ICs for high performance systems. There is no question that 3D ICs with through silicon vias (TSV) remain driven by concerns over astronomical lithography cost at future silicon technology nodes, requirements for high bandwidth between the memory and processor, lat... »