A recent IEEC and IEEE CPMT workshop held on October 16, 2013 at Binghamton University in New York examined the status of 2.5D and 3D ICs for high performance systems. There is no question that 3D ICs with through silicon vias (TSV) remain driven by concerns over astronomical lithography cost at future silicon technology nodes, requirements for high bandwidth between the memory and processor, latency issues, and the need for lower power solutions. While the drivers for 3D ICs remain constant, the timeline for its adoption keeps shifting out.
Issues highlighted at the workshop during the TechSearch International “report card” on the status of 3D ICs included: the ability of engineers to use design tools to enable a 3D IC solution, process issues such as the debonding step in wafer thinning and the yield of microbump assembly, thermal dissipation where logic and memory are stacked, and test methodology. It was noted that several companies are developing new materials that may improve process yield in the debonding step and improvements in equipment throughput are expected. EDA tool improvements to enable thermally aware designs are still required, but some promising developments from research at North Carolina State University were revealed. Comprehensive test methodologies are still critical, but new probe card solutions from Cascade Microtech, FormFactor, Micronics Japan, and Technoprobe have been introduced. While progress is underway in the development of 3D ICs, additional work is required, providing plenty of research opportunities for research organizations around the globe.
While there are some examples of 3D ICs in production today from Tezzaron, and an announcement of soon-to-be-available engineering samples of Micron’s Hybrid Memory Cube (HMC), these new architectures require longer adoption time than hyped-up market forecasters have lead us to believe. In the mean time, high-performance applications have been demonstrated using silicon interposers, or what is now commonly called 2.5D. Xilinx is shipping four FPGA products using silicon interposers, some with heterogeneous integration and others with homogeneous integration. Suresh Ramaligam, Senior Director, Package Design and Advanced Technology Development at Xilinx described some of these products and discussed the supply chain for their production.
Subramanian Iyer, an IBM fellow, described the need for “orthogonal scaling”. Iyer described attributes of the various interposer options and mentioned applications for high-performance products such as that of its foundry customer, Semtech. David McCann, Vice President, Packaging Technology at GLOBALFOUNDRIES described the drivers for interposers and the status of interposer product offers and how GLOBALFOUNDRIES works with OSATs. A number of companies show silicon interposer on their roadmaps for GPUs, ASICs, and other devices. Many applications depend on the availability of stacked memory, as was described in the discussion of die stacking and computing given by Michael SU, AMD Fellow. The panel session included a discussion on how companies with small volumes, such as medical applications from companies including GE and defense industry participants, can find a supply chain to allow them to move into production with 3D ICs and 2.5D.
With New York’s $1.5B public-private investment to create a large research organization in Utica, New York that is focused on packaging research and development, many companies are hopeful that an infrastructure will be developed to allow companies in the region to take advantage of advanced technologies. ~ J.V.