Xilinx

The Great Consolidation

The Great Consolidation

The recent MEPTEC – SEMI Symposium on “The Great Miniaturization” featured two days of talks on just that subject at the Biltmore Hotel in Santa Clara, CA, the week of November 9 2015. Thank you MEPTEC, thank you SEMI, and thank you to all speakers for the work you did preparing for, and then putting on, the symposium. It was my pleasure and my honor to moderate the panel discussion, which ... »

Xilinx: Ultrascale VU440 3D FPGA

Xilinx: Ultrascale VU440 3D FPGA

The Xilinx Ultrascale VU440 3D FPGA is constructed using “Xinterposer” 3D IC technology jointly developed by Xilinx and TSMC. It uses a low-k dielectric chip fabricated on 20nm silicon node with a total of 375,000 micron bumps stacked on 25mm x 45mm silicon interposer and assembled with CoWoS. The composite 3D FPGA consists of approximately 19 billion transistors. Testimonial: The Ultrasca... »

ECTC 2015: From the Tech Sessions Part 2

ECTC 2015: From the Tech Sessions Part 2

As promised in part 1 of my ECTC 2015 blog about this impressive conference, see below summaries of presentations I found very useful to contribute to the advancement of single- and multi-die packaging. To make it easier for the reader to dig deeper and review the entire paper, I included in every summary the paper number, as listed in the program and on the USB stick we received. As I mention in... »

Spotlight on FOWLP, Monolithic 3D IC and 3D TSVs

Spotlight on FOWLP, Monolithic 3D IC and 3D TSVs

Fan-out wafer level packaging’s star is clearly on the rise as a low-cost solution for consumer mobile products, and the semiconductor industry trade news has been buzzing with unsubstantiated claims that Qualcomm is ditching through silicon vias (TSVs) for monolithic 3D ICs (M3D) in its next generation of cell phones. Meanwhile, it seems 3D TSV technologies have been moved to the back burner un... »

Xilinx Ultrascale+: 3D on Steroids

Xilinx Ultrascale+: 3D on Steroids

Ever since 3D transistors (aka FinFETS or Intel’s Tri Gate) 3D NAND, and monolithic 3D IC processes joined the family of 3D integration technology possibilities, we’ve been careful to define them separately on 3D InCites. Some people have wondered if one will displace the other, or if these technologies would delay the adoption of 3D stacked ICs using TSVs. I maintain that these technologies h... »

The Small Scale Systems Integration and Packaging (S³IP) Center

3D ICs for High Performance Systems

A recent IEEC and IEEE CPMT workshop held on October 16, 2013 at Binghamton University in New York examined the status of 2.5D and 3D ICs for high performance systems. There is no question that 3D ICs with through silicon vias (TSV) remain driven by concerns over astronomical lithography cost at future silicon technology nodes, requirements for high bandwidth between the memory and processor, lat... »

And a Good Time was had by All – 3D InCites Awards Breakfast, 2013

And a Good Time was had by All – 3D InCites Awards Breakfast, 2013

Despite the chilly San Francisco morning temperatures, a sizable crowd of 2.5D and 3D enthusiasts gathered at the Impress Lounge to witness the inaugural 3D InCites Awards Breakfast, held July 11, 2013 during SEMICON West. For me, it was especially significant as it marked four years since I first launched 3D InCites at SEMICON West 2009. I felt truly honored to be surrounded by such industry elit... »

Momentum Builds for the 2013 3D InCites Awards

Momentum Builds for the 2013 3D InCites Awards

Subscribers are practically blowing up 3D InCites as they duke it out online and race the  July 3rd deadline for casting their ballots in the public opinion poll for this inaugural 3D InCites Awards; which is great because the first 3D InCites Awards Breakfast, co-presented by 3D InCites and TechSearch International, is fast approaching, and we’ve got an exciting program shaping up. We’re hap... »

Xilinx: Virtex-7 H580T

Xilinx: Virtex-7 H580T

Product Description The Virtex-7 H580T FPGA is the first 3D heterogeneous all programmable device, featuring up to eight 28 Gbps and 48 13.1 Gbps transceivers, making it the only single-chip solution to provide customers with the system integration to meet space, power and cost challenges of transitioning to 100G CFP2 optical modules. Testimonial As the world’s first 3D heterogeneous all program... »

Scaling 100G Wired Applications with Heterogeneous 3D FPGAs

Scaling 100G Wired Applications with Heterogeneous 3D FPGAs

By: Ehab Mohsen, Xilinx To address the insatiable demand for bandwidth, the communications industry is accelerating development of Nx100G line cards for networking systems. In order for equipment manufacturers to scale infrastructure economically and effectively, they must leverage the latest optical interconnect technologies, suh as CFP2 and in the future CFP4, to increase bandwidth while lowerin... »

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